diff options
| -rw-r--r-- | src/a.tex | 5 | ||||
| -rw-r--r-- | src/machine.tex | 2 | ||||
| -rw-r--r-- | src/memory.tex | 1 | ||||
| -rw-r--r-- | src/naming.tex | 1 | ||||
| -rw-r--r-- | src/riscv-spec.tex | 1 | ||||
| -rw-r--r-- | src/rvwmo.tex | 2 | ||||
| -rw-r--r-- | src/t.tex | 16 |
7 files changed, 3 insertions, 25 deletions
@@ -131,10 +131,7 @@ might cause a move away from DW-CAS. More generally, a multi-word atomic primitive is desirable, but there is still considerable debate about what form this should take, and -guaranteeing forward progress adds complexity to a system. Our -current thoughts are to include a small limited-capacity transactional -memory buffer along the lines of the original transactional memory -proposals as an optional standard extension ``T''. +guaranteeing forward progress adds complexity to a system. \end{commentary} The failure code with value 1 is reserved to encode an unspecified diff --git a/src/machine.tex b/src/machine.tex index 67a3a0c..d23a7a3 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -134,7 +134,7 @@ Bit & Character & Description \\ 16 & Q & Quad-precision floating-point extension \\ 17 & R & {\em Reserved} \\ 18 & S & Supervisor mode implemented \\ - 19 & T & {\em Tentatively reserved for Transactional Memory extension} \\ + 19 & T & {\em Reserved} \\ 20 & U & User mode implemented \\ 21 & V & {\em Tentatively reserved for Vector extension} \\ 22 & W & {\em Reserved} \\ diff --git a/src/memory.tex b/src/memory.tex index f35d247..35d458c 100644 --- a/src/memory.tex +++ b/src/memory.tex @@ -1328,7 +1328,6 @@ We expect that any or all of the following possible future extensions would be c \begin{itemize} \item `V' vector ISA extensions - \item A transactional memory subset of the `T' ISA extension \item `J' JIT extension \item Native encodings for load and store opcodes with {\em aq} and {\em rl} set \item Fences limited to certain addresses diff --git a/src/naming.tex b/src/naming.tex index fd9e9cf..c856e41 100644 --- a/src/naming.tex +++ b/src/naming.tex @@ -168,7 +168,6 @@ Quad-Precision Floating-Point & Q & D\\ Bit Manipulation & B & \\ Cryptography Extensions & K & \\ Dynamic Languages & J & \\ -Transactional Memory & T & \\ Packed-SIMD Extensions & P & \\ Vector Extensions & V & \\ User-Level Interrupts & N & \\ diff --git a/src/riscv-spec.tex b/src/riscv-spec.tex index b85c565..75c8dcc 100644 --- a/src/riscv-spec.tex +++ b/src/riscv-spec.tex @@ -94,7 +94,6 @@ Andrew Waterman and Krste Asanovi\'{c}, RISC-V Foundation, \specmonthyear. \input{c} \input{b} \input{j} -\input{t} \input{p} \input{v} \input{zam} diff --git a/src/rvwmo.tex b/src/rvwmo.tex index 228e582..f52ea8c 100644 --- a/src/rvwmo.tex +++ b/src/rvwmo.tex @@ -14,7 +14,7 @@ The standard ISA extension for misaligned atomics ``Zam'' (Chapter~\ref{sec:zam} The appendices to this specification provide both axiomatic and operational formalizations of the memory consistency model as well as additional explanatory material. \begin{commentary} - This chapter defines the memory model for regular main memory operations. The interaction of the memory model with I/O memory, instruction fetches, FENCE.I, page table walks, and SFENCE.VMA is not (yet) formalized. Some or all of the above may be formalized in a future revision of this specification. The RV128 base ISA and future ISA extensions such as the ``V'' vector, ``T'' transactional memory, and ``J'' JIT extensions will need to be incorporated into a future revision as well. + This chapter defines the memory model for regular main memory operations. The interaction of the memory model with I/O memory, instruction fetches, FENCE.I, page table walks, and SFENCE.VMA is not (yet) formalized. Some or all of the above may be formalized in a future revision of this specification. The RV128 base ISA and future ISA extensions such as the ``V'' vector and ``J'' JIT extensions will need to be incorporated into a future revision as well. Memory consistency models supporting overlapping memory accesses of different widths simultaneously remain an active area of academic research and are not yet fully understood. The specifics of how memory accesses of different sizes interact under RVWMO are specified to the best of our current abilities, but they are subject to revision should new issues be uncovered. \end{commentary} diff --git a/src/t.tex b/src/t.tex deleted file mode 100644 index d7f8efa..0000000 --- a/src/t.tex +++ /dev/null @@ -1,16 +0,0 @@ -\chapter{``T'' Standard Extension for Transactional Memory, Version 0.0} -\label{sec:tm} - -This chapter is a placeholder for a future standard extension to -provide transactional memory operations. - -\begin{commentary} -Despite much research over the last twenty years, and initial -commercial implementations, there is still much debate on the best way -to support atomic operations involving multiple addresses. - -Our current thoughts are to include a small limited-capacity -transactional memory buffer along the lines of the original -transactional memory proposals. -\end{commentary} - |