diff options
| -rw-r--r-- | build/Makefile | 4 | ||||
| -rw-r--r-- | src/machine.tex | 2 | ||||
| -rw-r--r-- | src/plic.tex | 2 | ||||
| -rw-r--r-- | src/supervisor.tex | 2 | ||||
| -rw-r--r-- | src/v.tex | 2 |
5 files changed, 6 insertions, 6 deletions
diff --git a/build/Makefile b/build/Makefile index ae4c9df..5182f32 100644 --- a/build/Makefile +++ b/build/Makefile @@ -1,8 +1,8 @@ #======================================================================= -# Makefile for generating latex documents +# Makefile for generating LaTeX documents #----------------------------------------------------------------------- # -# This is a simple makefile for generating latex documents. It will +# This is a simple makefile for generating LaTeX documents. It will # run bibtex, generate eps from xfig figures, and make pdfs. The # makefile supports builds in non-source directories: just make a # build directory, copy the makefile there, and change the srcdir diff --git a/src/machine.tex b/src/machine.tex index 57becad..f8a9296 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2346,7 +2346,7 @@ transitory state should not be visible to lower privilege levels. We categorize RISC-V caches into three types: {\em master-private}, {\em shared}, and {\em slave-private}. Master-private caches are attached to a single master agent, i.e., one that issues read/write -requests to the memory system. Shared caches are located inbetween +requests to the memory system. Shared caches are located between masters and slaves and may be hierarchically organized. Slave-private caches do not impact coherence, as they are local to a single slave and do not affect other PMAs at a master, so are not considered diff --git a/src/plic.tex b/src/plic.tex index 0b3419d..ebc3cf1 100644 --- a/src/plic.tex +++ b/src/plic.tex @@ -149,7 +149,7 @@ no longer requires service. If the global interrupt source was edge-triggered, the gateway will convert the first matching signal edge into an interrupt request. Depending on the design of the device and the interrupt handler, -inbetween sending an interrupt request and receiving notice of its +between sending an interrupt request and receiving notice of its handler's completion, the gateway might either ignore additional matching edges or increment a counter of pending interrupts. In either case, the next interrupt request will not be forwarded to the diff --git a/src/supervisor.tex b/src/supervisor.tex index fe00324..7da4cc2 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -161,7 +161,7 @@ The SIE bit enables or disables all interrupts in supervisor mode. When SIE is clear, interrupts are not taken while in supervisor mode. When the hart is running in user-mode, the value in SIE is ignored, and supervisor-level interrupts are enabled. The supervisor can disable -indivdual interrupt sources using the {\tt sie} register. +individual interrupt sources using the {\tt sie} register. The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode. When a trap is taken into supervisor @@ -438,7 +438,7 @@ no predicate registers are allocated. holding 5-bit vector register numbers for each supported type. Fields must either contain 0 indicating no vector registers are allocated for that type, or a vector register number greater - than all to the right. All vector register numbers inbetween two + than all to the right. All vector register numbers between two non-zero fields are allocated to the type with the higher vector register number. } \label{fig:vdcfg} |