diff options
| -rw-r--r-- | src/machine.tex | 31 | ||||
| -rw-r--r-- | src/supervisor.tex | 33 |
2 files changed, 39 insertions, 25 deletions
diff --git a/src/machine.tex b/src/machine.tex index 2af3382..cebd688 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1262,17 +1262,26 @@ interrupt controller, such as the standard platform-level interrupt controller specified in Chapter~\ref{plic}. The MEIE field in {\tt mie} enables machine external interrupts when set. -The SEIP field in {\tt mip} is a read-write bit that indicates -a supervisor-mode external interrupt is pending. SEIP may be written by -M-mode software to indicate to S-mode that an external interrupt is pending. -Additionally, the platform-level interrupt controller may generate supervior -external interrupts. When the SEIP bit is read with a CSRRW, CSRRS, or CSRRC -instruction, it appears to contain the logical-OR of the software-writable bit -and the interrupt signal from the interrupt controller. However, when the -SEIP bit is written with a CSRRS or CSRRC instruction, only the -software-writable portion of the SEIP bit affects the new value written to the -{\tt mip} CSR. The signal from the interrupt controller does {\em not} -participate in a CSRRS or CSRRC read-modify-write sequence. +The SEIP field in {\tt sip} contains a single read-write bit. SEIP +may be written by M-mode software to indicate to S-mode that an +external interrupt is pending. Additionally, the platform-level +interrupt controller may generate supervisor-level external interrupts. The +logical-OR of the software-writeable bit and the signal from the +external interrupt controller is used to generate external interrupts +to the supervisor. When the SEIP bit is read with a CSRRW, CSRRS, or +CSRRC instruction, the value returned in the {\tt rd} destination +register contains the logical-OR of the software-writable bit and the +interrupt signal from the interrupt controller. However, the value +used in the read-modify-write sequence of a CSRRS or CSRRC instruction +is only the software-writable SEIP bit, ignoring the interrupt value +from the external interrupt controller. + +\begin{commentary} + The SEIP field behavior is designed to allow a higher privilege + layer to mimic external interrupts cleanly, without losing any real + external interrupts. The behavior of the CSR instructions is + slightly modified from regular CSR accesses as a result. +\end{commentary} The UEIP field in {\tt mip} provides user-mode external interrupts when the N extension for user-mode interrupts is implemented. It is defined diff --git a/src/supervisor.tex b/src/supervisor.tex index 6a2d7a5..7a608f2 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -364,20 +364,25 @@ A supervisor-level external interrupt is pending if the SEIP bit in the when the SEIE bit in the {\tt sie} register is clear. The SBI should provide facilities to mask, unmask, and query the cause of external interrupts. -A user-level external interrupt is pending if the UEIP bit in the -{\tt sip} register is set. - -The UEIP field in {\tt sip} is a read-write bit that indicates a user-mode -external interrupt is pending. UEIP may be written by S-mode software to -indicate to S-mode that an external interrupt is pending. Additionally, the -platform-level interrupt controller may generate user-level external -interrupts. When the UEIP bit is read with a CSRRW, CSRRS, or CSRRC -instruction, it appears to contain the logical-OR of the software-writable bit -and the interrupt signal from the interrupt controller. However, when the UEIP -bit is written with a CSRRS or CSRRC instruction, only the software-writable -portion of the UEIP bit affects the new value written to the {\tt sip} CSR. -The user-level interrupt signal from the interrupt controller does {\em not} -participate in a CSRRS or CSRRC read-modify-write sequence. +The UEIP field in {\tt sip} contains a single read-write bit. UEIP +may be written by S-mode software to indicate to U-mode that an +external interrupt is pending. Additionally, the platform-level +interrupt controller may generate user-level external interrupts. The +logical-OR of the software-writeable bit and the signal from the +external interrupt controller are used to generate external interrupts +for user mode. When the UEIP bit is read with a CSRRW, CSRRS, or +CSRRC instruction, the value returned in the {\tt rd} destination +register contains the logical-OR of the software-writable bit and the +interrupt signal from the interrupt controller. However, the value +used in the read-modify-write sequence of a CSRRS or CSRRC instruction +is only the software-writable UEIP bit, ignoring the interrupt value +from the external interrupt controller. + +\begin{commentary} + Analogous to SEIP, the UIEP field behavior is designed to allow a + higher privilege layer to mimic external interrupts without losing + any real external interrupts. +\end{commentary} User-level external interrupts are disabled when the UEIE bit in the {\tt sie} register is clear. If the N extension for user-level interrupts is not |