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| author | Andrew Waterman <andrew@sifive.com> | 2017-04-07 15:26:39 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-04-07 15:26:39 -0700 |
| commit | e5eea2f305cbab2c0c78bbb0a982c6c954cd8683 (patch) | |
| tree | 63e3c8394176bcb826a065df8fd2d13bdcb3a3e4 /src | |
| parent | 4dcaa944ba40e074d25516a157fc37f7491b71cc (diff) | |
| download | riscv-isa-manual-e5eea2f305cbab2c0c78bbb0a982c6c954cd8683.zip riscv-isa-manual-e5eea2f305cbab2c0c78bbb0a982c6c954cd8683.tar.gz riscv-isa-manual-e5eea2f305cbab2c0c78bbb0a982c6c954cd8683.tar.bz2 | |
Reserve LSBs of stvec.
Diffstat (limited to 'src')
| -rw-r--r-- | src/supervisor.tex | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 983ef21..0d9de2c 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -222,17 +222,19 @@ SUM. The {\tt stvec} register is an XLEN-bit read/write register that holds the base address of the S-mode trap vector. When an exception occurs, the {\tt pc} is set to {\tt stvec}. The {\tt stvec} register is always aligned to -a 4-byte boundary. +a 4-byte boundary. The two least-significant bits of the {\tt stvec} register +are \wlrl\ and reserved for future use; standard software must only write +zeros to these bits. \begin{figure*}[h!] {\footnotesize \begin{center} -\begin{tabular}{J@{}F} +\begin{tabular}{J@{}R} \instbitrange{XLEN-1}{2} & \instbitrange{1}{0} \\ \hline \multicolumn{1}{|c|}{\tt Trap Vector Base Address} & -\multicolumn{1}{c|}{0} \\ +\multicolumn{1}{c|}{0 (\wlrl)} \\ \hline XLEN-2 & 2 \\ \end{tabular} |