From e5eea2f305cbab2c0c78bbb0a982c6c954cd8683 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Fri, 7 Apr 2017 15:26:39 -0700
Subject: Reserve LSBs of stvec.

---
 src/supervisor.tex | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/supervisor.tex b/src/supervisor.tex
index 983ef21..0d9de2c 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -222,17 +222,19 @@ SUM.
 The {\tt stvec} register is an XLEN-bit read/write register that holds the
 base address of the S-mode trap vector.  When an exception occurs, the {\tt
 pc} is set to {\tt stvec}.  The {\tt stvec} register is always aligned to
-a 4-byte boundary.
+a 4-byte boundary.  The two least-significant bits of the {\tt stvec} register
+are \wlrl\ and reserved for future use; standard software must only write
+zeros to these bits.
 
 \begin{figure*}[h!]
 {\footnotesize
 \begin{center}
-\begin{tabular}{J@{}F}
+\begin{tabular}{J@{}R}
 \instbitrange{XLEN-1}{2} &
 \instbitrange{1}{0} \\
 \hline
 \multicolumn{1}{|c|}{\tt Trap Vector Base Address} & 
-\multicolumn{1}{c|}{0} \\
+\multicolumn{1}{c|}{0 (\wlrl)} \\
 \hline
 XLEN-2 & 2 \\
 \end{tabular}
-- 
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