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| author | Bill Traynor <wmat@riscv.org> | 2022-08-24 14:18:27 -0400 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2022-08-24 14:18:27 -0400 |
| commit | 61b3e480006d98a73d6b03cfc141cf2ae0332b74 (patch) | |
| tree | 2d860816390fe5851b15ddd66c60d59da5341d99 /src/zicsr.adoc | |
| parent | 32e6108b425a3dd94807906201eb3fbf681abb89 (diff) | |
| download | riscv-isa-manual-61b3e480006d98a73d6b03cfc141cf2ae0332b74.zip riscv-isa-manual-61b3e480006d98a73d6b03cfc141cf2ae0332b74.tar.gz riscv-isa-manual-61b3e480006d98a73d6b03cfc141cf2ae0332b74.tar.bz2 | |
Clean up of redundant word Chapter and table ref.
When referencing an internal refernence it pulls in the full
Chapter name including the word Chapter, therefore including the
word Chapter is redundant.
Diffstat (limited to 'src/zicsr.adoc')
| -rw-r--r-- | src/zicsr.adoc | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/zicsr.adoc b/src/zicsr.adoc index 21fc3df..fcb19c4 100644 --- a/src/zicsr.adoc +++ b/src/zicsr.adoc @@ -5,7 +5,7 @@ RISC-V defines a separate address space of 4096 Control and Status registers associated with each hart. This chapter defines the full set of CSR instructions that operate on these CSRs. -[TIP] +[NOTE] ==== While CSRs are primarily used by the privileged architecture, there are several uses in unprivileged code including for counters and timers, and @@ -13,7 +13,7 @@ for floating-point status. The counters and timers are no longer considered mandatory parts of the standard base ISAs, and so the CSR instructions required to access them -have been moved out of Chapter <<rv32>> into this separate +have been moved out of <<rv32>> into this separate chapter. ==== @@ -74,8 +74,7 @@ Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of _rd_ and _rs1_ fields. [[csrsideeffects]] -.Conditions determining whether a CSR instruction reads or writes the -specified CSR. +.Conditions determining whether a CSR instruction reads or writes the specified CSR. [cols="^,^,^,^,^",options="header",] |=== 5+|Register operand @@ -104,7 +103,7 @@ CSR |CSRRSI/CSRRCI |– |No |Yes |Yes |=== -Table 11.1 summarizes the behavior of the CSR +<<csrsideeffects>> summarizes the behavior of the CSR instructions with respect to whether they read and/or write the CSR. For any event or consequence that occurs due to a CSR having a @@ -177,7 +176,7 @@ out-of-order by preceding instructions. (Note the distinction made earlier between side effects and indirect effects of CSR writes.) For the RVWMO memory consistency model -(Chapter <<memorymodel>>), CSR accesses are weakly +(<<memorymodel>>), CSR accesses are weakly ordered by default, so other harts or devices may observe CSR accesses in an order different from program order. In addition, CSR accesses are not ordered with respect to explicit memory accesses, unless a CSR |