Adding admonitions to match latex doc.

Added in NOTE and TIP admonitions to match latex doc indentations.

1 files changed, 27 insertions, 14 deletions

diff --git a/src/zfa.adoc b/src/zfa.adoc
index 1ca73ed..ebe6677 100644
--- a/src/zfa.adoc
+++ b/src/zfa.adoc
@@ -60,16 +60,21 @@ like FMV.W.X, but with _rs2_=1.
 |31 |_Canonical NaN_ |`0` |`11111111` |`100...000`
 |===
 
+[TIP]
+====
 The preferred assembly syntax for entries 1, 30, and 31 is `min`, `inf`,
 and `nan`, respectively. For entries 0 through 29 (including entry 1),
 the assembler will accept decimal constants in C-like syntax.
-
+====
+[TIP]
+====
 The set of 32 constants was chosen by examining floating-point
 libraries, including the C standard math library, and to optimize
 fixed-point to floating-point conversion.
 
 Entries 8–22 follow a regular encoding pattern. No entry sets mantissa
 bits other than the two most significant ones.
+====
 
 If the D extension is implemented, FLI.D performs the analogous
 operation, but loads a double-precision value into floating-point
@@ -92,10 +97,11 @@ half-precision. Furthermore, since latexmath:[$2^{16}$] is not
 representable in half-precision floating-point, entry 29 in the table
 instead loads positive infinity—i.e., it is redundant with entry 30.
 FLI.H is encoded like FLI.S, but with _fmt_=H.
-
+[NOTE]
+====
 Additionally, since latexmath:[$2^{-16}$] is a subnormal in
 half-precision, entry 1 is numerically greater than entry 2 for FLI.H.
-
+====
 The FLI._fmt_ instructions never set any floating-point exception flags.
 
 === Minimum and Maximum Instructions
@@ -115,10 +121,11 @@ analogously defined to operate on quad-precision numbers.
 
 These instructions are encoded like their FMIN and FMAX counterparts,
 but with instruction bit 13 set to 1.
-
+[NOTE]
+====
 These instructions implement the IEEE 754-2019 minimum and maximum
 operations.
-
+====
 === Round-to-Integer Instructions
 
 The FROUND.S instruction rounds the single-precision floating-point
@@ -146,11 +153,12 @@ respectively,
 If the Q extension is implemented, FROUND.Q and FROUNDNX.Q instructions
 are analogously defined to operate on quad-precision numbers. They are
 encoded like FCVT.Q.S, but with _rs2_=4 and 5, respectively,
-
+[NOTE]
+====
 The FROUNDNX._fmt_ instructions implement the IEEE 754-2019
 roundToIntegralExact operation, and the FROUND._fmt_ instructions
 implement the other operations in the roundToIntegral family.
-
+====
 === Modular Convert-to-Integer Instruction
 
 The FCVTMOD.W.D instruction is defined similarly to the FCVT.W.D
@@ -166,7 +174,8 @@ FCVT.W.D with the same input operand.
 This instruction is only provided if the D extension is implemented. It
 is encoded like FCVT.W.D, but with the rs2 field set to 8 and the _rm_
 field set to 1 (RTZ). Other _rm_ values are _reserved_.
-
+[TIP]
+====
 The assembly syntax requires the RTZ rounding mode to be explicitly
 specified, i.e., `fcvtmod.w.d rd, rs1, rtz`.
 
@@ -174,17 +183,18 @@ The FCVTMOD.W.D instruction was added principally to accelerate the
 processing of JavaScript `Number`s. `Number`s are double-precision
 values, but some operators implicitly truncate them to signed integers
 mod latexmath:[$2^{32}$].
-
+====
 === Move Instructions
 
 For RV32 only, if the D extension is implemented, the FMVH.X.D
 instruction moves bits 63:32 of floating-point register _rs1_ into
 integer register _rd_. It is encoded in the OP-FP major opcode with
 _funct3_=0, _rs2_=1, and _funct7_=1110001.
-
+[NOTE]
+====
 FMVH.X.D is used in conjunction with the existing FMV.X.W instruction to
 move a double-precision floating-point number to a pair of x-registers.
-
+====
 For RV32 only, if the D extension is implemented, the FMVP.D.X
 instruction moves a double-precision number from a pair of integer
 registers into a floating-point register. Integer registers _rs1_ and
@@ -196,10 +206,11 @@ For RV64 only, if the Q extension is implemented, the FMVH.X.Q
 instruction moves bits 127:64 of floating-point register _rs1_ into
 integer register _rd_. It is encoded in the OP-FP major opcode with
 _funct3_=0, _rs2_=1, and _funct7_=1110011.
-
+[NOTE]
+====
 FMVH.X.Q is used in conjunction with the existing FMV.X.D instruction to
 move a quad-precision floating-point number to a pair of x-registers.
-
+====
 For RV64 only, if the Q extension is implemented, the FMVP.Q.X
 instruction moves a double-precision number from a pair of integer
 registers into a floating-point register. Integer registers _rs1_ and
@@ -224,7 +235,9 @@ analogously defined to operate on quad-precision numbers.
 
 These instructions are encoded like their FLE and FLT counterparts, but
 with instruction bit 14 set to 1.
-
+[NOTE]
+====
 We do not expect analogous comparison instructions will be added to the
 vector ISA, since they can be reasonably efficiently emulated using
 masking.
+====
\ No newline at end of file