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| author | Bill Traynor <wmat@riscv.org> | 2022-11-14 13:17:30 -0500 |
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| committer | Bill Traynor <wmat@riscv.org> | 2022-11-14 13:17:30 -0500 |
| commit | 63aa6f6e1452bef07e41671f7cf4f5ed5ffea00d (patch) | |
| tree | 9a315fca9ee5b0d5390c072363914e67be90823d /src/zfa.adoc | |
| parent | ec4919caf5638e2d1c437391c6eab097e038aaec (diff) | |
| download | riscv-isa-manual-63aa6f6e1452bef07e41671f7cf4f5ed5ffea00d.zip riscv-isa-manual-63aa6f6e1452bef07e41671f7cf4f5ed5ffea00d.tar.gz riscv-isa-manual-63aa6f6e1452bef07e41671f7cf4f5ed5ffea00d.tar.bz2 | |
Fixed some formatting of single quotes and backticks.
Fixed some formatting of single quotes and backticks.
Diffstat (limited to 'src/zfa.adoc')
| -rw-r--r-- | src/zfa.adoc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/zfa.adoc b/src/zfa.adoc index 3e0a872..4fd236d 100644 --- a/src/zfa.adoc +++ b/src/zfa.adoc @@ -75,7 +75,7 @@ The set of 32 constants was chosen by examining floating-point libraries, including the C standard math library, and to optimize fixed-point to floating-point conversion. -Entries 8–22 follow a regular encoding pattern. No entry sets mantissa +Entries 8-22 follow a regular encoding pattern. No entry sets mantissa bits other than the two most significant ones. ==== @@ -133,7 +133,7 @@ operations. The FROUND.S instruction rounds the single-precision floating-point number in floating-point register _rs1_ to an integer, according to the -rounding mode specified in the instruction’s _rm_ field. It then writes +rounding mode specified in the instruction's _rm_ field. It then writes that integer, represented as a single-precision floating-point number, to floating-point register _rd_. Zero and infinite inputs are copied to _rd_ unmodified. Signaling NaN inputs cause the invalid operation @@ -166,7 +166,7 @@ implement the other operations in the roundToIntegral family. The FCVTMOD.W.D instruction is defined similarly to the FCVT.W.D instruction, with the following differences. FCVTMOD.W.D always rounds -towards zero. Bits 31:0 are taken from the rounded, unbounded two’s +towards zero. Bits 31:0 are taken from the rounded, unbounded two's complement result, then sign-extended to XLEN bits and written to integer register _rd_. latexmath:[$\pm\infty$] and NaN are converted to zero. @@ -183,7 +183,7 @@ The assembly syntax requires the RTZ rounding mode to be explicitly specified, i.e., `fcvtmod.w.d rd, rs1, rtz`. The FCVTMOD.W.D instruction was added principally to accelerate the -processing of JavaScript `Number`s. `Number`s are double-precision +processing of JavaScript `Numbers`. `Numbers` are double-precision values, but some operators implicitly truncate them to signed integers mod latexmath:[$2^{32}$]. ==== |