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| author | Andrew Waterman <andrew@sifive.com> | 2021-11-15 17:14:39 -0800 |
|---|---|---|
| committer | Bill Traynor <btraynor@gmail.com> | 2022-07-26 11:19:26 -0400 |
| commit | 12edf349c0c8f38d8c55bb3193ed117ba657426b (patch) | |
| tree | deb980989ebbb326026e0796477955904ca13893 /src/supervisor.tex | |
| parent | 5196b7856480c8a683ab32dc44d4c0921d3ca33a (diff) | |
| download | riscv-isa-manual-12edf349c0c8f38d8c55bb3193ed117ba657426b.zip riscv-isa-manual-12edf349c0c8f38d8c55bb3193ed117ba657426b.tar.gz riscv-isa-manual-12edf349c0c8f38d8c55bb3193ed117ba657426b.tar.bz2 | |
Fix typo
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index c78dd84..7e09107 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1236,7 +1236,7 @@ SFENCE.VMA instructions as having {\em rs1}={\tt x0} and/or {\em rs2}={\tt x0}. For example, simpler implementations can ignore the virtual address in {\em rs1} and the ASID value in {\em rs2} and always perform a global fence. The choice not to raise an exception when an invalid virtual -address is held in {\em rs1} facilicates this type of simplification. +address is held in {\em rs1} facilitates this type of simplification. \end{commentary} An implicit read of the memory-management data structures may return any |