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| author | Andrew Waterman <andrew@sifive.com> | 2018-12-04 00:21:34 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-12-04 00:21:34 -0800 |
| commit | 5f111da2fadf82865af018e473ce728ebfc20622 (patch) | |
| tree | 9a196fa1762bef48b0228aa684574903d2212fe5 /src/supervisor.tex | |
| parent | 8e52ffa49d09437c69fec6e173dfbddeb9e8ea1a (diff) | |
| download | riscv-isa-manual-5f111da2fadf82865af018e473ce728ebfc20622.zip riscv-isa-manual-5f111da2fadf82865af018e473ce728ebfc20622.tar.gz riscv-isa-manual-5f111da2fadf82865af018e473ce728ebfc20622.tar.bz2 | |
Version of priv spec ready for ratification process
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 2087c39..53d7dad 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -595,7 +595,7 @@ The Interrupt bit in the {\tt scause} register is set if the trap was caused by an interrupt. The Exception Code field contains a code identifying the last exception. Table~\ref{scauses} lists the possible exception codes for the current supervisor ISAs, in -descending order of priority. The Exception Code is an \wlrl\ field, +descending order of priority. The Exception Code is a \wlrl\ field, so is only guaranteed to hold supported exception codes. \begin{figure*}[h!] |