From 5f111da2fadf82865af018e473ce728ebfc20622 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Tue, 4 Dec 2018 00:21:34 -0800
Subject: Version of priv spec ready for ratification process

---
 src/supervisor.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/supervisor.tex')

diff --git a/src/supervisor.tex b/src/supervisor.tex
index 2087c39..53d7dad 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -595,7 +595,7 @@ The Interrupt bit in the {\tt scause} register is set if the
 trap was caused by an interrupt. The Exception Code field
 contains a code identifying the last exception.  Table~\ref{scauses}
 lists the possible exception codes for the current supervisor ISAs, in
-descending order of priority.  The Exception Code is an \wlrl\ field,
+descending order of priority.  The Exception Code is a \wlrl\ field,
 so is only guaranteed to hold supported exception codes.
 
 \begin{figure*}[h!]
-- 
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