diff options
| author | Andrew Waterman <andrew@sifive.com> | 2023-10-30 17:38:29 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-10-30 17:38:29 -0700 |
| commit | ea578803bfdedfdeb77f996062b7ad4c82369ba6 (patch) | |
| tree | b176053fae5578fa463631fef9e005271d09b98d /src/supervisor.adoc | |
| parent | 38d5bfd49e0837341e4b87cf2deb6c0975998d6a (diff) | |
| download | riscv-isa-manual-ea578803bfdedfdeb77f996062b7ad4c82369ba6.zip riscv-isa-manual-ea578803bfdedfdeb77f996062b7ad4c82369ba6.tar.gz riscv-isa-manual-ea578803bfdedfdeb77f996062b7ad4c82369ba6.tar.bz2 | |
Clarify meaning of "platform or custom use"
Resolves #1128
Diffstat (limited to 'src/supervisor.adoc')
| -rw-r--r-- | src/supervisor.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/supervisor.adoc b/src/supervisor.adoc index f8aa5c5..a860ce5 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -225,7 +225,7 @@ SXLEN-bit read/write register containing interrupt enable bits. Interrupt cause number _i_ (as reported in CSR `scause`, <<scause>>) corresponds with bit _i_ in both `sip` and `sie`. Bits 15:0 are allocated to standard interrupt causes only, while -bits 16 and above are designated for platform or custom use. +bits 16 and above are designated for platform use. .Supervisor interrupt-pending register (`sip`). include::images/bytefield/sip.edn[] |