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| author | Bill Traynor <wmat@riscv.org> | 2024-04-11 06:29:05 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-11 06:29:05 -0400 |
| commit | 382fd8bd3e83105582057f494983424c5d9b6526 (patch) | |
| tree | 3a1fe971885bf6a367186780152bb1a3bebcd8ed /src/supervisor.adoc | |
| parent | 525cf683e337e43153c20aa63f4f5449d28cfabf (diff) | |
| parent | 83fc7c1e9eca8a3abb77266c97acbf07275d2ce0 (diff) | |
| download | riscv-isa-manual-382fd8bd3e83105582057f494983424c5d9b6526.zip riscv-isa-manual-382fd8bd3e83105582057f494983424c5d9b6526.tar.gz riscv-isa-manual-382fd8bd3e83105582057f494983424c5d9b6526.tar.bz2 | |
Merge pull request #1339 from riscv/chapter-titles-cleanupriscv-isa-release-382fd8b-2024-04-11
Chapter titles cleanup
Diffstat (limited to 'src/supervisor.adoc')
| -rw-r--r-- | src/supervisor.adoc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/supervisor.adoc b/src/supervisor.adoc index 63bef5e..636c3bf 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -1670,7 +1670,7 @@ in <<sv32algorithm>>, except LEVELS equals 5 and PTESIZE equals 8. [[svnapot]] -== "Svnapot" Standard Extension for NAPOT Translation Contiguity, Version 1.0 +== "Svnapot" Extension for NAPOT Translation Contiguity, Version 1.0 In Sv39, Sv48, and Sv57, when a PTE has N=1, the PTE represents a translation that is part of a range of contiguous virtual-to-physical @@ -1836,7 +1836,7 @@ first step. ==== [[svpbmt]] -== "Svpbmt" Standard Extension for Page-Based Memory Types, Version 1.0 +== "Svpbmt" Extension for Page-Based Memory Types, Version 1.0 In Sv39, Sv48, and Sv57, bits 62-61 of a leaf page table entry indicate the use of page-based memory types that override the PMA(s) for the @@ -1962,7 +1962,7 @@ attributes used by accesses to the page in question. Otherwise, the intermediate attributes are used as the final set of attributes. [[svinval]] -== "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0 +== "Svinval" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0 The Svinval extension splits SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA instructions into finer-grained invalidation and ordering operations @@ -2054,7 +2054,7 @@ instructions as no-ops. ==== [[sec:svadu]] -== "Svadu" Standard Extension for Hardware Updating of A/D Bits, Version 1.0 +== "Svadu" Extension for Hardware Updating of A/D Bits, Version 1.0 The Svadu extension adds support and CSR controls for hardware updating of PTE A/D bits. @@ -2069,7 +2069,7 @@ exceptions when A/D bits need be set, instead takes effect. The Svade extension is also defined in <<translation>>. [[sec:svvptc]] -== "Svvptc" Standard Extension for Eliding Memory-Management Fences on Making PTEs Valid, Version 1.0 +== "Svvptc" Extension for Eliding Memory-Management Fences on Making PTEs Valid, Version 1.0 When the Svvptc extension is implemented, explicit stores that update the Valid bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart will @@ -2096,7 +2096,7 @@ fence instructions outweighs the occasional cost of a gratuitous page-fault. //// [[sec:ssqosid]] -== "Ssqosid" Standard Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 +== "Ssqosid" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 Quality of Service (QoS) is defined as the minimal end-to-end performance guaranteed in advance by a service level agreement (SLA) to a workload. |