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| author | Kersten Richter <kersten@riscv.org> | 2024-04-18 07:19:16 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-18 07:19:16 -0500 |
| commit | b0a6a3886bd003a5686243871fa936613390445e (patch) | |
| tree | 9ed28e44ebc1178a0acecfe99a8d0efcc2dfc936 /src/sstc.adoc | |
| parent | e825d9f423d16a0dd997c89883004319ec704af2 (diff) | |
| download | riscv-isa-manual-b0a6a3886bd003a5686243871fa936613390445e.zip riscv-isa-manual-b0a6a3886bd003a5686243871fa936613390445e.tar.gz riscv-isa-manual-b0a6a3886bd003a5686243871fa936613390445e.tar.bz2 | |
Update src/sstc.adoc
Signed-off-by: Kersten Richter <kersten@riscv.org>
Diffstat (limited to 'src/sstc.adoc')
| -rw-r--r-- | src/sstc.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/sstc.adoc b/src/sstc.adoc index fe8d8f6..5efcd01 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -85,7 +85,7 @@ cleared by writing `stimecmp` with a value greater than the current time value. This extension modifies the description of the STIP/STIE bits in these registers as follows: -Bits `sip.STIP` and `sie.STIE` are the interrupt-pending and interrupt-enable bits +Bits `sip`.STIP and `sie`.STIE are the interrupt-pending and interrupt-enable bits for supervisor level timer interrupts. If implemented, STIP is read-only in sip, and is either set and cleared by the execution environment (if `stimecmp` is not implemented), or reflects the timer interrupt signal resulting from |