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| author | Andrew Waterman <andrew@sifive.com> | 2024-04-04 16:48:20 -0700 |
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| committer | Andrew Waterman <andrew@sifive.com> | 2024-04-04 16:48:20 -0700 |
| commit | 42019faba3e90ef350e3ade7aee72fc88813a2af (patch) | |
| tree | 23a98334a5e3fa855b5fcdad25c91f7f7b61a09e /src/sscofpmf.adoc | |
| parent | 4af7149ea31fb60d30581e16faa3885fe5d00fb3 (diff) | |
| download | riscv-isa-manual-42019faba3e90ef350e3ade7aee72fc88813a2af.zip riscv-isa-manual-42019faba3e90ef350e3ade7aee72fc88813a2af.tar.gz riscv-isa-manual-42019faba3e90ef350e3ade7aee72fc88813a2af.tar.bz2 | |
Move mhpmevent CSR numbers to main CSR table
Diffstat (limited to 'src/sscofpmf.adoc')
| -rw-r--r-- | src/sscofpmf.adoc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/sscofpmf.adoc b/src/sscofpmf.adoc index 0a7af58..0d69c2e 100644 --- a/src/sscofpmf.adoc +++ b/src/sscofpmf.adoc @@ -49,8 +49,7 @@ be used for event selection purposes. On RV32 only, accesses to the mcycle, minstret, mhpmcounter__n__, and mhpmevent__n__ CSRs access the low 32 bits, while accesses to the mcycleh, minstreth, mhpmcounter__n__h, and mhpmevent__n__h CSRs access bits 63–32 of the -corresponding counter or event selector. The proposed CSR numbers for -mhpmevent__n__h are 0x723 - 0x73F. +corresponding counter or event selector. The following bits are added to `mhpmevent`: |