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| author | Bill Traynor <wmat@riscv.org> | 2023-01-31 14:21:34 -0500 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2023-01-31 14:21:34 -0500 |
| commit | 24be8094955ffc7b3dab22d71c49b4d548e65480 (patch) | |
| tree | d11e22c0c2ec7451c8c86d15627d912648e35aef /src/rvwmo.adoc | |
| parent | b6f44baccdca4430de538b7af719f7e308b69017 (diff) | |
| download | riscv-isa-manual-24be8094955ffc7b3dab22d71c49b4d548e65480.zip riscv-isa-manual-24be8094955ffc7b3dab22d71c49b4d548e65480.tar.gz riscv-isa-manual-24be8094955ffc7b3dab22d71c49b4d548e65480.tar.bz2 | |
Formatting tables
Fixing the tables so they align like in latex
Diffstat (limited to 'src/rvwmo.adoc')
| -rw-r--r-- | src/rvwmo.adoc | 68 |
1 files changed, 34 insertions, 34 deletions
diff --git a/src/rvwmo.adoc b/src/rvwmo.adoc index 75a98c6..6401759 100644 --- a/src/rvwmo.adoc +++ b/src/rvwmo.adoc @@ -520,77 +520,77 @@ register(s) to destination register(s) as specified |=== .RV64I Base Integer Instruction Set -[%autowidth,float="center",align="center",cols="<,<,<,<",options="header"] +[%autowidth,float="center",align="center",cols="<,<,<,<,<",options="header"] |=== -||Source Registers |Destination Registers |Accumulating CSRs +||Source Registers |Destination Registers |Accumulating CSRs| -|_LWU_ † |_rs1_ ^A^ |_rd_ | +|_LWU_ † |_rs1_ ^A^ |_rd_ || -|_LD_ † |_rs1_ ^A^ |_rd_ | +|_LD_ † |_rs1_ ^A^ |_rd_ || -|SD |_rs1_ ^A^, _rs2_ ^D^ | +|SD |_rs1_ ^A^, _rs2_ ^D^ ||| -|SLLI | _rs1_ | _rd_ | +|SLLI | _rs1_ | _rd_ || -|SRLI | _rs1_ | _rd_ | +|SRLI | _rs1_ | _rd_ || -|SRAI | _rs1_ | _rd_ | +|SRAI | _rs1_ | _rd_ || -|ADDIW | _rs1_ | _rd_ | +|ADDIW | _rs1_ | _rd_ || -|SLLIW | _rs1_ | _rd_ | +|SLLIW | _rs1_ | _rd_ || -|SRLIW | _rs1_ | _rd_ | +|SRLIW | _rs1_ | _rd_ || -|SRAIW | _rs1_ | _rd_ | +|SRAIW | _rs1_ | _rd_ || -|ADDW | _rs1_, _rs2_ |_rd_ | +|ADDW | _rs1_, _rs2_ |_rd_ || -|SUBW | _rs1_, _rs2_ |_rd_ | +|SUBW | _rs1_, _rs2_ |_rd_ || -|SLLW | _rs1_, _rs2_ |_rd_ | +|SLLW | _rs1_, _rs2_ |_rd_ || -|SRLW | _rs1_, _rs2_ |_rd_ | +|SRLW | _rs1_, _rs2_ |_rd_ || -|SRAW | _rs1_, _rs2_ |_rd_ | +|SRAW | _rs1_, _rs2_ |_rd_ || |=== .RV32M Standard Extension -[%autowidth,float="center",align="center",cols="<,<,<,<",options="header"] +[%autowidth,float="center",align="center",cols="<,<,<,<,<",options="header"] |=== -| |Source Regisers |Destination Registers |Accumulating CSRs +| |Source Regisers |Destination Registers |Accumulating CSRs| -|MUL | _rs1_, _rs2_ |_rd_ | +|MUL | _rs1_, _rs2_ |_rd_ || -|MULH | _rs1_, _rs2_ |_rd_ | +|MULH | _rs1_, _rs2_ |_rd_ || -|MULHSU |_rs1_, _rs2_ |_rd_ | +|MULHSU |_rs1_, _rs2_ |_rd_ || -|MULHU |_rs1_, _rs2_ |_rd_ | +|MULHU |_rs1_, _rs2_ |_rd_ || -|DIV |_rs1_, _rs2_ |_rd_ | +|DIV |_rs1_, _rs2_ |_rd_ || -|DIVU |_rs1_, _rs2_ |_rd_ | +|DIVU |_rs1_, _rs2_ |_rd_ || -|REM |_rs1_, _rs2_ |_rd_ | +|REM |_rs1_, _rs2_ |_rd_ || -|REMU |_rs1_, _rs2_ |_rd_ | +|REMU |_rs1_, _rs2_ |_rd_ || |=== .RV64M Standard Extension -[%autowidth,float="center",align="center",cols="<,<,<,<",options="header"] +[%autowidth,float="center",align="center",cols="<,<,<,<,<",options="header"] |=== -||Source Registers |Destination Registers |Accumulating CSRs +||Source Registers |Destination Registers |Accumulating CSRs| -|MULW |_rs1_, _rs2_ |_rd_ | +|MULW |_rs1_, _rs2_ |_rd_ || -|DIVW |_rs1_, _rs2_ |_rd_ | +|DIVW |_rs1_, _rs2_ |_rd_ || -|DIVUW |_rs1_, _rs2_ |_rd_ | +|DIVUW |_rs1_, _rs2_ |_rd_ || -|REMW |_rs1_, _rs2_ |_rd_ | +|REMW |_rs1_, _rs2_ |_rd_ || -|REMUW |_rs1_, _rs2_ |_rd_ | +|REMUW |_rs1_, _rs2_ |_rd_ || |=== .RV32A Standard Extension |