Removed remaining latex.

Removed remaining latex.

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diff --git a/src/rvc-instr-table.tex b/src/rvc-instr-table.tex
deleted file mode 100644
index 68dab32..0000000
--- a/src/rvc-instr-table.tex
+++ /dev/null
@@ -1,537 +0,0 @@
-
-\begin{table}[h]
-\begin{small}
-\begin{center}
-\begin{tabular}{p{0in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}l}
-& & & & & & & & & & \\
-                      &
-\instbit{15} &
-\instbit{14} &
-\instbit{13} &
-\multicolumn{1}{c}{\instbit{12}} &
-\instbit{11} &
-\instbit{10} &
-\instbit{9} &
-\instbit{8} &
-\instbit{7} &
-\instbit{6} &
-\multicolumn{1}{c}{\instbit{5}} &
-\instbit{4} &
-\instbit{3} &
-\instbit{2} &
-\instbit{1} &
-\instbit{0} \\
-\cline{2-17}
-
-
-&
-\multicolumn{3}{|c|}{000} &
-\multicolumn{8}{c|}{0} &
-\multicolumn{3}{c|}{0} &
-\multicolumn{2}{c|}{00} & {\em Illegal instruction} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{000} &
-\multicolumn{8}{c|}{nzuimm[5:4$\vert$9:6$\vert$2$\vert$3]} &
-\multicolumn{3}{c|}{\rdprime} &
-\multicolumn{2}{c|}{00} & C.ADDI4SPN {\em \tiny (RES, nzuimm=0)} \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{001} &
-\multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{\rsoneprime} &
-\multicolumn{2}{c|}{uimm[7:6]} &
-\multicolumn{3}{c|}{\rdprime} &
-\multicolumn{2}{c|}{00} & C.FLD {\em \tiny (RV32/64)}\\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{001} &
-\multicolumn{3}{c|}{uimm[5:4$\vert$8]} &
-\multicolumn{3}{c|}{\rsoneprime} &
-\multicolumn{2}{c|}{uimm[7:6]} &
-\multicolumn{3}{c|}{\rdprime} &
-\multicolumn{2}{c|}{00} & C.LQ {\em \tiny (RV128)}\\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{010} &
-\multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{\rsoneprime} &
-\multicolumn{2}{c|}{uimm[2$\vert$6]} &
-\multicolumn{3}{c|}{\rdprime} &
-\multicolumn{2}{c|}{00} & C.LW \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{011} &
-\multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{\rsoneprime} &
-\multicolumn{2}{c|}{uimm[2$\vert$6]} &
-\multicolumn{3}{c|}{\rdprime} &
-\multicolumn{2}{c|}{00} & C.FLW {\em \tiny (RV32)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{011} &
-\multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{\rsoneprime} &
-\multicolumn{2}{c|}{uimm[7:6]} &
-\multicolumn{3}{c|}{\rdprime} &
-\multicolumn{2}{c|}{00} & C.LD {\em \tiny (RV64/128)}\\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{11}{c|}{---} &
-\multicolumn{2}{c|}{00} & {\em Reserved} \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{101} &
-\multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{\rsoneprime} &
-\multicolumn{2}{c|}{uimm[7:6]} &
-\multicolumn{3}{c|}{\rstwoprime} &
-\multicolumn{2}{c|}{00} & C.FSD {\em \tiny (RV32/64)}\\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{101} &
-\multicolumn{3}{c|}{uimm[5:4$\vert$8]} &
-\multicolumn{3}{c|}{\rsoneprime} &
-\multicolumn{2}{c|}{uimm[7:6]} &
-\multicolumn{3}{c|}{\rstwoprime} &
-\multicolumn{2}{c|}{00} & C.SQ {\em \tiny (RV128)}\\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{110} &
-\multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{\rsoneprime} &
-\multicolumn{2}{c|}{uimm[2$\vert$6]} &
-\multicolumn{3}{c|}{\rstwoprime} &
-\multicolumn{2}{c|}{00} & C.SW \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{111} &
-\multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{\rsoneprime} &
-\multicolumn{2}{c|}{uimm[2$\vert$6]} &
-\multicolumn{3}{c|}{\rstwoprime} &
-\multicolumn{2}{c|}{00} & C.FSW {\em \tiny (RV32)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{111} &
-\multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{\rsoneprime} &
-\multicolumn{2}{c|}{uimm[7:6]} &
-\multicolumn{3}{c|}{\rstwoprime} &
-\multicolumn{2}{c|}{00} & C.SD {\em \tiny (RV64/128)}\\
-\cline{2-17}
-
-\end{tabular}
-\end{center}
-\end{small}
-\caption{Instruction listing for RVC, Quadrant 0.}
-\label{rvc-instr-table0}
-\end{table}
-
-\begin{table}[h]
-\begin{small}
-\begin{center}
-\begin{tabular}{p{0in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}l}
-& & & & & & & & & & \\
-                      &
-\instbit{15} &
-\instbit{14} &
-\instbit{13} &
-\multicolumn{1}{c}{\instbit{12}} &
-\instbit{11} &
-\instbit{10} &
-\instbit{9} &
-\instbit{8} &
-\instbit{7} &
-\instbit{6} &
-\multicolumn{1}{c}{\instbit{5}} &
-\instbit{4} &
-\instbit{3} &
-\instbit{2} &
-\instbit{1} &
-\instbit{0} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{000} &
-\multicolumn{1}{c|}{nzimm[5]} &
-\multicolumn{5}{c|}{0} &
-\multicolumn{5}{c|}{nzimm[4:0]} &
-\multicolumn{2}{c|}{01} & C.NOP {\em \tiny (HINT, nzimm$\neq$0) } \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{000} &
-\multicolumn{1}{c|}{nzimm[5]} &
-\multicolumn{5}{c|}{rs1/rd$\neq$0} &
-\multicolumn{5}{c|}{nzimm[4:0]} &
-\multicolumn{2}{c|}{01} & C.ADDI {\em \tiny (HINT, nzimm=0)} \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{001} &
-\multicolumn{11}{c|}{imm[11$\vert$4$\vert$9:8$\vert$10$\vert$6$\vert$7$\vert$3:1$\vert$5]} &
-\multicolumn{2}{c|}{01} & C.JAL {\em \tiny (RV32)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{001} &
-\multicolumn{1}{c|}{imm[5]} &
-\multicolumn{5}{c|}{rs1/rd$\neq$0} &
-\multicolumn{5}{c|}{imm[4:0]} &
-\multicolumn{2}{c|}{01} & C.ADDIW {\em \tiny (RV64/128; RES, rd=0)} \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{010} &
-\multicolumn{1}{c|}{imm[5]} &
-\multicolumn{5}{c|}{rd$\neq$0} &
-\multicolumn{5}{c|}{imm[4:0]} &
-\multicolumn{2}{c|}{01} & C.LI {\em \tiny (HINT, rd=0)} \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{011} &
-\multicolumn{1}{c|}{nzimm[9]} &
-\multicolumn{5}{c|}{2} &
-\multicolumn{5}{c|}{nzimm[4$\vert$6$\vert$8:7$\vert$5]} &
-\multicolumn{2}{c|}{01} & C.ADDI16SP {\em \tiny (RES, nzimm=0)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{011} &
-\multicolumn{1}{c|}{nzimm[17]} &
-\multicolumn{5}{c|}{rd$\neq$$\{0,2\}$} &
-\multicolumn{5}{c|}{nzimm[16:12]} &
-\multicolumn{2}{c|}{01} & C.LUI {\em \tiny (RES, nzimm=0; HINT, rd=0)}\\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{nzuimm[5]} &
-\multicolumn{2}{c|}{00} &
-\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
-\multicolumn{5}{c|}{nzuimm[4:0]} &
-\multicolumn{2}{c|}{01} & C.SRLI {\em \tiny (RV32 Custom, nzuimm[5]=1)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{0} &
-\multicolumn{2}{c|}{00} &
-\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
-\multicolumn{5}{c|}{0} &
-\multicolumn{2}{c|}{01} & C.SRLI64 {\em \tiny (RV128; RV32/64 HINT)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{nzuimm[5]} &
-\multicolumn{2}{c|}{01} &
-\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
-\multicolumn{5}{c|}{nzuimm[4:0]} &
-\multicolumn{2}{c|}{01} & C.SRAI {\em \tiny (RV32 Custom, nzuimm[5]=1)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{0} &
-\multicolumn{2}{c|}{01} &
-\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
-\multicolumn{5}{c|}{0} &
-\multicolumn{2}{c|}{01} & C.SRAI64 {\em \tiny (RV128; RV32/64 HINT)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{imm[5]} &
-\multicolumn{2}{c|}{10} &
-\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
-\multicolumn{5}{c|}{imm[4:0]} &
-\multicolumn{2}{c|}{01} & C.ANDI \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{0} &
-\multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
-\multicolumn{2}{c|}{00} &
-\multicolumn{3}{c|}{\rstwoprime} &
-\multicolumn{2}{c|}{01} & C.SUB \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{0} &
-\multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
-\multicolumn{2}{c|}{01} &
-\multicolumn{3}{c|}{\rstwoprime} &
-\multicolumn{2}{c|}{01} & C.XOR \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{0} &
-\multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
-\multicolumn{2}{c|}{10} &
-\multicolumn{3}{c|}{\rstwoprime} &
-\multicolumn{2}{c|}{01} & C.OR \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{0} &
-\multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
-\multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{\rstwoprime} &
-\multicolumn{2}{c|}{01} & C.AND \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{1} &
-\multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
-\multicolumn{2}{c|}{00} &
-\multicolumn{3}{c|}{\rstwoprime} &
-\multicolumn{2}{c|}{01} & C.SUBW {\em \tiny (RV64/128; RV32 RES)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{1} &
-\multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
-\multicolumn{2}{c|}{01} &
-\multicolumn{3}{c|}{\rstwoprime} &
-\multicolumn{2}{c|}{01} & C.ADDW {\em \tiny (RV64/128; RV32 RES)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{1} &
-\multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{---} &
-\multicolumn{2}{c|}{10} &
-\multicolumn{3}{c|}{---} &
-\multicolumn{2}{c|}{01} & {\em Reserved} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{1} &
-\multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{---} &
-\multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{---} &
-\multicolumn{2}{c|}{01} & {\em Reserved} \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{101} &
-\multicolumn{11}{c|}{imm[11$\vert$4$\vert$9:8$\vert$10$\vert$6$\vert$7$\vert$3:1$\vert$5]} &
-\multicolumn{2}{c|}{01} & C.J \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{110} &
-\multicolumn{3}{c|}{imm[8$\vert$4:3]} &
-\multicolumn{3}{c|}{\rsoneprime} &
-\multicolumn{5}{c|}{imm[7:6$\vert$2:1$\vert$5]} &
-\multicolumn{2}{c|}{01} & C.BEQZ \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{111} &
-\multicolumn{3}{c|}{imm[8$\vert$4:3]} &
-\multicolumn{3}{c|}{\rsoneprime} &
-\multicolumn{5}{c|}{imm[7:6$\vert$2:1$\vert$5]} &
-\multicolumn{2}{c|}{01} & C.BNEZ \\
-\cline{2-17}
-  
-
-\end{tabular}
-\end{center}
-\end{small}
-\caption{Instruction listing for RVC, Quadrant 1.}
-\label{rvc-instr-table1}
-\end{table}
-
-\begin{table}[h]
-\begin{small}
-\begin{center}
-\begin{tabular}{p{0in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}l}
-& & & & & & & & & & \\
-                      &
-\instbit{15} &
-\instbit{14} &
-\instbit{13} &
-\multicolumn{1}{c}{\instbit{12}} &
-\instbit{11} &
-\instbit{10} &
-\instbit{9} &
-\instbit{8} &
-\instbit{7} &
-\instbit{6} &
-\multicolumn{1}{c}{\instbit{5}} &
-\instbit{4} &
-\instbit{3} &
-\instbit{2} &
-\instbit{1} &
-\instbit{0} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{000} &
-\multicolumn{1}{c|}{nzuimm[5]} &
-\multicolumn{5}{c|}{rs1/rd$\neq$0} &
-\multicolumn{5}{c|}{nzuimm[4:0]} &
-\multicolumn{2}{c|}{10} & C.SLLI {\em \tiny (HINT, rd=0; RV32 Custom, nzuimm[5]=1)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{000} &
-\multicolumn{1}{c|}{0} &
-\multicolumn{5}{c|}{rs1/rd$\neq$0} &
-\multicolumn{5}{c|}{0} &
-\multicolumn{2}{c|}{10} & C.SLLI64 {\em \tiny (RV128; RV32/64 HINT; HINT, rd=0)} \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{001} &
-\multicolumn{1}{c|}{uimm[5]} &
-\multicolumn{5}{c|}{rd} &
-\multicolumn{5}{c|}{uimm[4:3$\vert$8:6]} &
-\multicolumn{2}{c|}{10} & C.FLDSP {\em \tiny (RV32/64)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{001} &
-\multicolumn{1}{c|}{uimm[5]} &
-\multicolumn{5}{c|}{rd$\neq$0} &
-\multicolumn{5}{c|}{uimm[4$\vert$9:6]} &
-\multicolumn{2}{c|}{10} & C.LQSP {\em \tiny (RV128; RES, rd=0)} \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{010} &
-\multicolumn{1}{c|}{uimm[5]} &
-\multicolumn{5}{c|}{rd$\neq$0} &
-\multicolumn{5}{c|}{uimm[4:2$\vert$7:6]} &
-\multicolumn{2}{c|}{10} & C.LWSP {\em \tiny (RES, rd=0)} \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{011} &
-\multicolumn{1}{c|}{uimm[5]} &
-\multicolumn{5}{c|}{rd} &
-\multicolumn{5}{c|}{uimm[4:2$\vert$7:6]} &
-\multicolumn{2}{c|}{10} & C.FLWSP {\em \tiny (RV32)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{011} &
-\multicolumn{1}{c|}{uimm[5]} &
-\multicolumn{5}{c|}{rd$\neq$0} &
-\multicolumn{5}{c|}{uimm[4:3$\vert$8:6]} &
-\multicolumn{2}{c|}{10} & C.LDSP {\em \tiny (RV64/128; RES, rd=0)} \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{0} &
-\multicolumn{5}{c|}{rs1$\neq$0} &
-\multicolumn{5}{c|}{0} &
-\multicolumn{2}{c|}{10} & C.JR {\em \tiny (RES, rs1=0)}\\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{0} &
-\multicolumn{5}{c|}{rd$\neq$0} &
-\multicolumn{5}{c|}{rs2$\neq$0} &
-\multicolumn{2}{c|}{10} & C.MV {\em \tiny (HINT, rd=0)}\\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{1} &
-\multicolumn{5}{c|}{0} &
-\multicolumn{5}{c|}{0} &
-\multicolumn{2}{c|}{10} & C.EBREAK \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{1} &
-\multicolumn{5}{c|}{rs1$\neq$0} &
-\multicolumn{5}{c|}{0} &
-\multicolumn{2}{c|}{10} & C.JALR \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{100} &
-\multicolumn{1}{c|}{1} &
-\multicolumn{5}{c|}{rs1/rd$\neq$0} &
-\multicolumn{5}{c|}{rs2$\neq$0} &
-\multicolumn{2}{c|}{10} & C.ADD {\em \tiny (HINT, rd=0)} \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{101} &
-\multicolumn{6}{c|}{uimm[5:3$\vert$8:6]} &
-\multicolumn{5}{c|}{rs2} &
-\multicolumn{2}{c|}{10} & C.FSDSP {\em \tiny (RV32/64)}\\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{101} &
-\multicolumn{6}{c|}{uimm[5:4$\vert$9:6]} &
-\multicolumn{5}{c|}{rs2} &
-\multicolumn{2}{c|}{10} & C.SQSP {\em \tiny (RV128)}\\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{110} &
-\multicolumn{6}{c|}{uimm[5:2$\vert$7:6]} &
-\multicolumn{5}{c|}{rs2} &
-\multicolumn{2}{c|}{10} & C.SWSP \\
-\whline{2-17}
-
-&
-\multicolumn{3}{|c|}{111} &
-\multicolumn{6}{c|}{uimm[5:2$\vert$7:6]} &
-\multicolumn{5}{c|}{rs2} &
-\multicolumn{2}{c|}{10} & C.FSWSP {\em \tiny (RV32)} \\
-\cline{2-17}
-
-&
-\multicolumn{3}{|c|}{111} &
-\multicolumn{6}{c|}{uimm[5:3$\vert$8:6]} &
-\multicolumn{5}{c|}{rs2} &
-\multicolumn{2}{c|}{10} & C.SDSP {\em \tiny (RV64/128)}\\
-\cline{2-17}
-
-\end{tabular}
-\end{center}
-\end{small}
-\caption{Instruction listing for RVC, Quadrant 2.}
-\label{rvc-instr-table2}
-\end{table}