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| author | Andrew Waterman <andrew@sifive.com> | 2023-02-05 17:46:42 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-02-05 17:46:42 -0800 |
| commit | 6cab541b60afc594042ebbc91d962e3399191c98 (patch) | |
| tree | 4eb90e9e3eb728d0cdb2d752d99d24070b28c8e9 /src/rv64.adoc | |
| parent | 64dd976a8f3270e8c4819f315cd739c012aa9c9b (diff) | |
| download | riscv-isa-manual-6cab541b60afc594042ebbc91d962e3399191c98.zip riscv-isa-manual-6cab541b60afc594042ebbc91d962e3399191c98.tar.gz riscv-isa-manual-6cab541b60afc594042ebbc91d962e3399191c98.tar.bz2 | |
Split SLLIW etc. off from SLLI table
Diffstat (limited to 'src/rv64.adoc')
| -rw-r--r-- | src/rv64.adoc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/rv64.adoc b/src/rv64.adoc index cf6911c..f33bf8c 100644 --- a/src/rv64.adoc +++ b/src/rv64.adoc @@ -50,8 +50,8 @@ immediate to register _rs1_ and produces the proper sign-extension of a writes the sign-extension of the lower 32 bits of register _rs1_ into register _rd_ (assembler pseudoinstruction SEXT.W). -include::images/wavedrom/rv64i-addiw.adoc[] -[[rv64i-addiw]] +include::images/wavedrom/rv64i-slli.adoc[] +[[rv64i-slli]] //.RV64I register-immediate (descr ADDIW) instructions Shifts by a constant are encoded as a specialization of the I-type @@ -67,6 +67,9 @@ copied into the vacated upper bits). (((RV64I, SRLIW))) (((RV64I, RV64I-only))) +include::images/wavedrom/rv64i-slliw.adoc[] +[[rv64i-slliw]] + SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with |