From 6cab541b60afc594042ebbc91d962e3399191c98 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Sun, 5 Feb 2023 17:46:42 -0800
Subject: Split SLLIW etc. off from SLLI table

---
 src/rv64.adoc | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'src/rv64.adoc')

diff --git a/src/rv64.adoc b/src/rv64.adoc
index cf6911c..f33bf8c 100644
--- a/src/rv64.adoc
+++ b/src/rv64.adoc
@@ -50,8 +50,8 @@ immediate to register _rs1_ and produces the proper sign-extension of a
 writes the sign-extension of the lower 32 bits of register _rs1_ into
 register _rd_ (assembler pseudoinstruction SEXT.W).
 
-include::images/wavedrom/rv64i-addiw.adoc[]
-[[rv64i-addiw]]
+include::images/wavedrom/rv64i-slli.adoc[]
+[[rv64i-slli]]
 //.RV64I register-immediate (descr ADDIW) instructions
 
 Shifts by a constant are encoded as a specialization of the I-type
@@ -67,6 +67,9 @@ copied into the vacated upper bits).
 (((RV64I, SRLIW)))
 (((RV64I, RV64I-only)))
 
+include::images/wavedrom/rv64i-slliw.adoc[]
+[[rv64i-slliw]]
+
 SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously
 defined but operate on 32-bit values and sign-extend their 32-bit
 results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with
-- 
cgit v1.1

