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| author | elisa <elisa@riscv.org> | 2021-10-28 14:25:12 -0700 |
|---|---|---|
| committer | elisa <elisa@riscv.org> | 2021-10-28 14:25:12 -0700 |
| commit | 364c03e71fd206c030d1ffb13b50f91ffd910be4 (patch) | |
| tree | bd84680727581685c68b8389ee44d4dd6833357c /src/rv32e.adoc | |
| parent | 3daeab91d68fefef377e204f0bc47018c605aeb0 (diff) | |
| download | riscv-isa-manual-364c03e71fd206c030d1ffb13b50f91ffd910be4.zip riscv-isa-manual-364c03e71fd206c030d1ffb13b50f91ffd910be4.tar.gz riscv-isa-manual-364c03e71fd206c030d1ffb13b50f91ffd910be4.tar.bz2 | |
formatting refinements
Diffstat (limited to 'src/rv32e.adoc')
| -rw-r--r-- | src/rv32e.adoc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/rv32e.adoc b/src/rv32e.adoc index 775771f..afa30ca 100644 --- a/src/rv32e.adoc +++ b/src/rv32e.adoc @@ -23,7 +23,7 @@ an RV64E to reduce context state for highly threaded 64-bit processors. === RV32E Programmers’ Model RV32E reduces the integer register count to 16 general-purpose -registers, (`x0`–`x15`), where `x0` is a dedicated zero register. +registers, (`x0–x15`), where `x0` is a dedicated zero register. [TIP] ==== @@ -42,7 +42,7 @@ RV32I. (((RV32E, difference from RV32I))) RV32E uses the same instruction-set encoding as RV32I, except that only -registers `x0`–`x15` are provided. Any future standard extensions will +registers `x0–x15` are provided. Any future standard extensions will not make use of the instruction bits freed up by the reduced register-specifier fields and so these are designated for custom extensions. |