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| author | elisa <elisa@riscv.org> | 2021-09-28 09:26:30 -0700 |
|---|---|---|
| committer | elisa <elisa@riscv.org> | 2021-09-28 09:26:30 -0700 |
| commit | c755f05b62e435e43de88abf4b68b1575e239957 (patch) | |
| tree | 89f7f4cbe788006f4a9cb2ef40a8e5b06b9cde47 /src/rv32.adoc | |
| parent | 937f16832c71e9b1c794fe02a11c7ebb7837ead8 (diff) | |
| download | riscv-isa-manual-c755f05b62e435e43de88abf4b68b1575e239957.zip riscv-isa-manual-c755f05b62e435e43de88abf4b68b1575e239957.tar.gz riscv-isa-manual-c755f05b62e435e43de88abf4b68b1575e239957.tar.bz2 | |
some table fixes and additions of missing formatting
Diffstat (limited to 'src/rv32.adoc')
| -rw-r--r-- | src/rv32.adoc | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/rv32.adoc b/src/rv32.adoc index b035fe3..4fcd166 100644 --- a/src/rv32.adoc +++ b/src/rv32.adoc @@ -193,7 +193,6 @@ include::images/wavedrom/immediate.adoc[] .Immediate variants for I, S, B, U, and J image::image_placeholder.png[] - Sign-extension is one of the most critical operations on immediates (particularly for XLEN latexmath:[$>$]32), and in RISC-V the sign bit for all immediates is always held in bit 31 of the instruction to allow @@ -278,7 +277,6 @@ include::images/wavedrom/int-comp-slli-srli-srai.adoc[] .Integer register-immediate, SLLI, SRLI, SRAI image::image_placeholder.png[] - Shifts by a constant are encoded as a specialization of the I-type format. The operand to be shifted is in _rs1_, and the shift amount is encoded in the lower 5 bits of the I-immediate field. The right shift @@ -287,13 +285,11 @@ shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits). - include::images/wavedrom/int-comp-lui-aiupc.adoc[] [[int-comp-lui-aiupc]] .Integer register-immediate, U-immediate image::image_placeholder.png[] - LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUI places the 32-bit U-immediate value into the destination register _rd_, filling in the lowest 12 bits with zeros. @@ -918,7 +914,7 @@ hints, security tags, and instrumentation flags for simulation/emulation. ==== -// this table isn't quite right and needs to be fixed--some rows might not have landed properly. It needs to be checked cell-by cell. +// this table might still have some problems--some rows might not have landed properly. It needs to be checked cell-by cell. [[t-rv32i-hints]] .RV32I HINT instructions. @@ -986,3 +982,4 @@ simulation/emulation. |SLTU |_rd_=`x0` |latexmath:[$2^{10}$] |=== + |