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| author | Bill Traynor <wmat@riscv.org> | 2023-01-03 10:05:50 -0500 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2023-01-03 10:05:50 -0500 |
| commit | 329e041a4368fc4f1a8b5f2084e731485e632376 (patch) | |
| tree | 5c6e2406b948209126bb83ad06a483a3257d86d3 /src/rv32.adoc | |
| parent | 7ce46cdc29824a99c71205336a71bb50c894a841 (diff) | |
| download | riscv-isa-manual-329e041a4368fc4f1a8b5f2084e731485e632376.zip riscv-isa-manual-329e041a4368fc4f1a8b5f2084e731485e632376.tar.gz riscv-isa-manual-329e041a4368fc4f1a8b5f2084e731485e632376.tar.bz2 | |
Removed linenums from codeblock.
Removed linenums from codeblock to match LaTeX.
Diffstat (limited to 'src/rv32.adoc')
| -rw-r--r-- | src/rv32.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/rv32.adoc b/src/rv32.adoc index f6d506e..b4b814b 100644 --- a/src/rv32.adoc +++ b/src/rv32.adoc @@ -922,7 +922,7 @@ Because the RISC-V base ISAs do not provide more than one EBREAK instruction, RISC-V semihosting uses a special sequence of instructions to distinguish a semihosting EBREAK from a debugger inserted EBREAK. -[source%linenums,asm] +[source,asm] .... slli x0, x0, 0x1f # Entry NOP ebreak # Break to debugger |