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| author | Bill Traynor <wmat@riscv.org> | 2023-01-03 14:47:59 -0500 |
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| committer | Bill Traynor <wmat@riscv.org> | 2023-01-03 14:47:59 -0500 |
| commit | bb5b64f2836e8dc3852a55af9281b9b2ed0df8d7 (patch) | |
| tree | ba735374aaf253618a9657ec6dbe39155f84de41 /src/rv128.adoc | |
| parent | 8e45213bb9c3deae43e93c87fca0fbe41798cb96 (diff) | |
| download | riscv-isa-manual-bb5b64f2836e8dc3852a55af9281b9b2ed0df8d7.zip riscv-isa-manual-bb5b64f2836e8dc3852a55af9281b9b2ed0df8d7.tar.gz riscv-isa-manual-bb5b64f2836e8dc3852a55af9281b9b2ed0df8d7.tar.bz2 | |
Fixed quote/attribution to be asciidoc.
Fixed quote/attribution to be asciidoc.
Diffstat (limited to 'src/rv128.adoc')
| -rw-r--r-- | src/rv128.adoc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/rv128.adoc b/src/rv128.adoc index 2440753..a8e42ca 100644 --- a/src/rv128.adoc +++ b/src/rv128.adoc @@ -1,11 +1,10 @@ [[rv128]] == RV128I Base Integer Instruction Set, Version 1.7 -==== "There is only one mistake that can be made in computer design that is difficult to recover from—not having enough address bits for memory -addressing and memory management." Bell and Strecker, ISCA-3, 1976. -==== +addressing and memory management." +-- Bell and Strecker, ISCA-3, 1976. This chapter describes RV128I, a variant of the RISC-V ISA supporting a flat 128-bit address space. The variant is a straightforward |