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| author | Andrew Waterman <andrew@sifive.com> | 2024-04-23 14:06:03 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-04-23 14:06:03 -0700 |
| commit | 1153db082b34950dc282bc9b87727199c005c3ad (patch) | |
| tree | b21fddcc7a1fd2ca4ae3e122179f8430f7378ba6 /src/rnmi.adoc | |
| parent | d8e41f9af1259bef31369383c356c69cefcdea83 (diff) | |
| download | riscv-isa-manual-1153db082b34950dc282bc9b87727199c005c3ad.zip riscv-isa-manual-1153db082b34950dc282bc9b87727199c005c3ad.tar.gz riscv-isa-manual-1153db082b34950dc282bc9b87727199c005c3ad.tar.bz2 | |
Clarify a possible RNMI exception trap handler configuration
Diffstat (limited to 'src/rnmi.adoc')
| -rw-r--r-- | src/rnmi.adoc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/rnmi.adoc b/src/rnmi.adoc index 24b5e66..9343976 100644 --- a/src/rnmi.adoc +++ b/src/rnmi.adoc @@ -33,6 +33,9 @@ The RNMI interrupt trap handler address is implementation-defined. RNMI also has an associated exception trap handler address, which is implementation defined. +NOTE: For example, some implementations might use the address specified +in `mtvec` as the RNMI exception trap handler. + === RNMI CSRs This proposal adds additional M-mode CSRs to enable a resumable |