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| author | Andrew Waterman <andrew@sifive.com> | 2018-12-02 16:18:54 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-12-02 17:05:29 -0800 |
| commit | 67611c065bb470f592ebf81b9499f1a3515f95d1 (patch) | |
| tree | e85778108c5fc3708d4623c6ebc74935d80e33a9 /src/priv-preface.tex | |
| parent | 1e47b3ec566142846c4e42cfa80e406b77e6395a (diff) | |
| download | riscv-isa-manual-67611c065bb470f592ebf81b9499f1a3515f95d1.zip riscv-isa-manual-67611c065bb470f592ebf81b9499f1a3515f95d1.tar.gz riscv-isa-manual-67611c065bb470f592ebf81b9499f1a3515f95d1.tar.bz2 | |
Clarify misaligned-AMO emulation scheme
Diffstat (limited to 'src/priv-preface.tex')
| -rw-r--r-- | src/priv-preface.tex | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 12292ce..ed41a6e 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -20,9 +20,7 @@ architecture proposal. Changes from version 1.10 include: \item Required all harts in a system to employ the same PTE-update scheme as each other. \item Rectified an editing error that misdescribed the mechanism by which {\tt mstatus}.{\em x}IE is written upon an exception. -\item Added the constraint that if a PMA supports LR, SC, or AMOs, but traps - misaligned LR, SC, or AMOs, then it also must trap - misaligned loads and stores. +\item Described scheme for emulating misaligned AMOs. \item Specified the behavior of the {\tt misa} and {\em x}{\tt epc} registers in systems with variable IALIGN. \item Specified the behavior of writing self-contradictory values to the |