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| author | Andrew Waterman <andrew@sifive.com> | 2017-11-09 17:20:29 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-11-09 17:20:29 -0800 |
| commit | 32b74b7a02e492c48a910ba0d20bcc52155b0616 (patch) | |
| tree | 671303c0c0b3b2dc32b8f6211131af8225fa5d05 /src/priv-preface.tex | |
| parent | 059f64c941856f249d8a0647e23e150dbdb1f62c (diff) | |
| download | riscv-isa-manual-32b74b7a02e492c48a910ba0d20bcc52155b0616.zip riscv-isa-manual-32b74b7a02e492c48a910ba0d20bcc52155b0616.tar.gz riscv-isa-manual-32b74b7a02e492c48a910ba0d20bcc52155b0616.tar.bz2 | |
Make MPP/SPP WARL fields
Diffstat (limited to 'src/priv-preface.tex')
| -rw-r--r-- | src/priv-preface.tex | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 5e04665..095e374 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -11,6 +11,7 @@ architecture proposal. Changes from version 1.10 include: \item Specified which interrupt sources are reserved for standard use. \item The virtual-memory system no longer permits supervisor mode to execute instructions from user pages, regardless of the SUM setting. +\item Made the {\tt mstatus}.MPP field \warl, rather than \wlrl. \end{itemize} \newpage |