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| author | Daniel Lustig <dlustig@nvidia.com> | 2021-06-02 09:49:23 -0400 |
|---|---|---|
| committer | Daniel Lustig <dlustig@nvidia.com> | 2021-06-02 09:49:23 -0400 |
| commit | e2f81a1791cf5f0483200c3c37150d0f2eccc485 (patch) | |
| tree | 12b9364c66ecf3a7d9c5538f0234a5f02343d0da /src/priv-preface.tex | |
| parent | 883bd183513ccdfed62a31d862d1c843aed3e3d0 (diff) | |
| parent | 58b9433f58d5b199a7e470f11cb7474368cb7d11 (diff) | |
| download | riscv-isa-manual-e2f81a1791cf5f0483200c3c37150d0f2eccc485.zip riscv-isa-manual-e2f81a1791cf5f0483200c3c37150d0f2eccc485.tar.gz riscv-isa-manual-e2f81a1791cf5f0483200c3c37150d0f2eccc485.tar.bz2 | |
Merge branch 'virtual-memory' into Svnapot
Diffstat (limited to 'src/priv-preface.tex')
| -rw-r--r-- | src/priv-preface.tex | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 14593a8..0ca835c 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -55,6 +55,7 @@ Additionally, the following compatible changes have been made since version \begin{itemize} \parskip 0pt \itemsep 1pt +\item Moved N extension into its own chapter. \item Defined the RV32-only CSR {\tt mstatush}, which contains most of the same fields as the upper 32 bits of RV64's {\tt mstatus}. \item Permitted the unconditional delegation of less-privileged interrupts. @@ -66,12 +67,13 @@ Additionally, the following compatible changes have been made since version \item An additional 48 optional PMP registers have been defined. \item Added the Svnapot Standard Extension draft, along with the N bit in Sv39, Sv48, and Sv57 PTEs -\item Added the C bit to Sv39 and Sv48 PTEs to indicate custom encodings. \item Described the behavior of address-translation caches a little more explicitly. \item Slightly relaxed the atomicity requirement for A and D bit updates performed by the implementation. \item Added Sv57 and Sv57x4 address translation modes. +\item Software breakpoint exceptions are permitted to write either 0 + or the PC to {\em x}\/{\tt tval}. \end{itemize} Finally, the hypervisor architecture proposal has been extensively revised. @@ -119,7 +121,7 @@ Changes from version 1.10 include: \item SFENCE.VMA semantics have been clarified. \item Made the {\tt mstatus}.MPP field \warl, rather than \wlrl. \item Made the unused {\em x}{\tt ip} fields \wpri, rather than \wiri. -\item Made the unused {\tt misa} fields \wlrl, rather than \wiri. +\item Made the unused {\tt misa} fields \warl, rather than \wiri. \item Made the unused {\tt pmpaddr} and {\tt pmpcfg} fields \warl, rather than \wiri. \item Required all harts in a system to employ the same PTE-update scheme as each other. \item Rectified an editing error that misdescribed the mechanism by which |