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| author | Andrew Waterman <andrew@sifive.com> | 2024-01-29 23:17:17 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-01-29 23:17:17 -0800 |
| commit | d88c7d1931c6a5987894013f514429b82877a027 (patch) | |
| tree | 463974faa40b634a93292650360de94dc4abb67a /src/priv-preface.adoc | |
| parent | c33a55eea6ee2dc2de4ff6ac6e183458450b82a3 (diff) | |
| download | riscv-isa-manual-d88c7d1931c6a5987894013f514429b82877a027.zip riscv-isa-manual-d88c7d1931c6a5987894013f514429b82877a027.tar.gz riscv-isa-manual-d88c7d1931c6a5987894013f514429b82877a027.tar.bz2 | |
Reorder changelog
Diffstat (limited to 'src/priv-preface.adoc')
| -rw-r--r-- | src/priv-preface.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc index 3c481bf..4591c9f 100644 --- a/src/priv-preface.adoc +++ b/src/priv-preface.adoc @@ -47,6 +47,7 @@ implemented. * Defined the RV32-only `medelegh` and `hedelegh` CSRs. * Defined the misaligned atomicity granule PMA. * Reserved interrupt 13 for forthcoming counter-overflow interrupt extension. +* Defined hardware error and software check exception codes. * Specified synchronization requirements when changing the PBMTE fields in `menvcfg` and `henvcfg`. * Clarified that "platform- or custom-use" interrupts are actually @@ -60,7 +61,6 @@ in `menvcfg` and `henvcfg`. * Clarified that, for a given exception cause, `__x__tval` might sometimes be set to a nonzero value but sometimes not. * Clarified exception behavior of unimplemented or inaccessible CSRs. -* Defined hardware error and software check exception codes. [.big]*_Preface to Version 20211203_* |