diff options
author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-01-21 09:17:55 +0900 |
---|---|---|
committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-01-21 09:17:55 +0900 |
commit | 5f481d6f558959b78c2fb75d3b5889d5e9ec2e7f (patch) | |
tree | fc2d1c002f35b847bf43187c52e2e79c6353ec8c /src/priv-instr-table.tex | |
parent | d5cb720d688b20e606b21530c0b79d59cf08880a (diff) | |
download | riscv-isa-manual-5f481d6f558959b78c2fb75d3b5889d5e9ec2e7f.zip riscv-isa-manual-5f481d6f558959b78c2fb75d3b5889d5e9ec2e7f.tar.gz riscv-isa-manual-5f481d6f558959b78c2fb75d3b5889d5e9ec2e7f.tar.bz2 |
Update Instruction Tables based on riscv-opcodes
Now, the entire instruction tables are generated by riscv-opcodes.
CMO instructions (Zicbo[mpz] extensions) are manually removed because
they are not yet defined in the ISA Manual.
Diffstat (limited to 'src/priv-instr-table.tex')
-rw-r--r-- | src/priv-instr-table.tex | 135 |
1 files changed, 71 insertions, 64 deletions
diff --git a/src/priv-instr-table.tex b/src/priv-instr-table.tex index ab51dd2..304c04c 100644 --- a/src/priv-instr-table.tex +++ b/src/priv-instr-table.tex @@ -54,7 +54,7 @@ \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{1110011} & SRET \\ \cline{2-11} - + & \multicolumn{4}{|c|}{0011000} & @@ -64,14 +64,14 @@ \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{1110011} & MRET \\ \cline{2-11} - + & \multicolumn{10}{c}{} & \\ & \multicolumn{10}{c}{\bf Interrupt-Management Instructions} & \\ \cline{2-11} - + & \multicolumn{4}{|c|}{0001000} & @@ -81,14 +81,14 @@ \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{1110011} & WFI \\ \cline{2-11} - + & \multicolumn{10}{c}{} & \\ & \multicolumn{10}{c}{\bf Supervisor Memory-Management Instructions} & \\ \cline{2-11} - + & \multicolumn{4}{|c|}{0001001} & @@ -98,44 +98,14 @@ \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{1110011} & SFENCE.VMA \\ \cline{2-11} - - -& -\multicolumn{4}{|c|}{0001011} & -\multicolumn{2}{c|}{rs2} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{1110011} & SINVAL.VMA \\ -\cline{2-11} - - -& -\multicolumn{4}{|c|}{0001100} & -\multicolumn{2}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{1110011} & SFENCE.W.INVAL \\ -\cline{2-11} - -& -\multicolumn{4}{|c|}{0001100} & -\multicolumn{2}{c|}{00001} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{1110011} & SFENCE.INVAL.IR \\ -\cline{2-11} - & \multicolumn{10}{c}{} & \\ & \multicolumn{10}{c}{\bf Hypervisor Memory-Management Instructions} & \\ \cline{2-11} - + & \multicolumn{4}{|c|}{0010001} & @@ -145,7 +115,7 @@ \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{1110011} & HFENCE.VVMA \\ \cline{2-11} - + & \multicolumn{4}{|c|}{0110001} & @@ -155,27 +125,7 @@ \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{1110011} & HFENCE.GVMA \\ \cline{2-11} - -& -\multicolumn{4}{|c|}{0010011} & -\multicolumn{2}{c|}{rs2} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{1110011} & HINVAL.VVMA \\ -\cline{2-11} - - -& -\multicolumn{4}{|c|}{0110011} & -\multicolumn{2}{c|}{rs2} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{1110011} & HINVAL.GVMA \\ -\cline{2-11} - & \multicolumn{10}{c}{} & \\ @@ -225,22 +175,22 @@ & -\multicolumn{4}{|c|}{0110010} & -\multicolumn{2}{c|}{00011} & +\multicolumn{4}{|c|}{0110100} & +\multicolumn{2}{c|}{00000} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{100} & \multicolumn{1}{c|}{rd} & -\multicolumn{1}{c|}{1110011} & HLVX.HU \\ +\multicolumn{1}{c|}{1110011} & HLV.W \\ \cline{2-11} & -\multicolumn{4}{|c|}{0110100} & -\multicolumn{2}{c|}{00000} & +\multicolumn{4}{|c|}{0110010} & +\multicolumn{2}{c|}{00011} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{100} & \multicolumn{1}{c|}{rd} & -\multicolumn{1}{c|}{1110011} & HLV.W \\ +\multicolumn{1}{c|}{1110011} & HLVX.HU \\ \cline{2-11} @@ -321,9 +271,66 @@ \cline{2-11} +& +\multicolumn{10}{c}{} & \\ +& +\multicolumn{10}{c}{\bf \emph{Svinval} Memory-Management Extension} & \\ +\cline{2-11} + + +& +\multicolumn{4}{|c|}{0001011} & +\multicolumn{2}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{1110011} & SINVAL.VMA \\ +\cline{2-11} + + +& +\multicolumn{4}{|c|}{0001100} & +\multicolumn{2}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{1110011} & SFENCE.W.INVAL \\ +\cline{2-11} + + +& +\multicolumn{4}{|c|}{0001100} & +\multicolumn{2}{c|}{00001} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{1110011} & SFENCE.INVAL.IR \\ +\cline{2-11} + + +& +\multicolumn{4}{|c|}{0010011} & +\multicolumn{2}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{1110011} & HINVAL.VVMA \\ +\cline{2-11} + + +& +\multicolumn{4}{|c|}{0110011} & +\multicolumn{2}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{1110011} & HINVAL.GVMA \\ +\cline{2-11} + + \end{tabular} \end{center} \end{small} \caption{RISC-V Privileged Instructions} \end{table} - + |