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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-21 22:32:31 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-21 22:36:48 -0800 |
| commit | e7b9fbbc1f540f7d1ff51971846b24d4fa3ca4d7 (patch) | |
| tree | 8e0969a9d477a5c1476395fa60529950718d47c0 /src/priv-csrs.tex | |
| parent | b38e6f31254797d4bd18ef3cba2eb022faa82bff (diff) | |
| download | riscv-isa-manual-e7b9fbbc1f540f7d1ff51971846b24d4fa3ca4d7.zip riscv-isa-manual-e7b9fbbc1f540f7d1ff51971846b24d4fa3ca4d7.tar.gz riscv-isa-manual-e7b9fbbc1f540f7d1ff51971846b24d4fa3ca4d7.tar.bz2 | |
Move counter-enable CSRs to trap-setup CSR space
Diffstat (limited to 'src/priv-csrs.tex')
| -rw-r--r-- | src/priv-csrs.tex | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index 34499a4..c982127 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -195,6 +195,7 @@ Number & Privilege & Name & Description \\ \tt 0x103 & SRW &\tt sideleg & Supervisor interrupt delegation register. \\ \tt 0x104 & SRW &\tt sie & Supervisor interrupt-enable register. \\ \tt 0x105 & SRW &\tt stvec & Supervisor trap handler base address. \\ +\tt 0x106 & SRW &\tt scounteren & Supervisor counter enable. \\ \hline \multicolumn{4}{|c|}{Supervisor Trap Handling} \\ \hline @@ -208,10 +209,6 @@ Number & Privilege & Name & Description \\ \hline \tt 0x180 & SRW &\tt sptbr & Page-table base register. \\ \hline -\multicolumn{4}{|c|}{Supervisor Counter Setup} \\ -\hline -\tt 0x120 & SRW &\tt scounteren & Supervisor counter enable. \\ -\hline \end{tabular} \end{center} \caption{Currently allocated RISC-V supervisor-level CSR addresses.} @@ -231,6 +228,7 @@ Number & Privilege & Name & Description \\ \tt 0x203 & HRW &\tt hideleg & Hypervisor interrupt delegation register. \\ \tt 0x204 & HRW &\tt hie & Hypervisor interrupt-enable register. \\ \tt 0x205 & HRW &\tt htvec & Hypervisor trap handler base address. \\ +\tt 0x206 & HRW &\tt hcounteren & Hypervisor counter enable. \\ \hline \multicolumn{4}{|c|}{Hypervisor Trap Handling} \\ \hline @@ -244,10 +242,6 @@ Number & Privilege & Name & Description \\ \hline \tt 0x28X & TBD & TBD & TBD. \\ \hline -\multicolumn{4}{|c|}{Hypervisor Counter Setup} \\ -\hline -\tt 0x220 & HRW &\tt hcounteren & Hypervisor counter enable. \\ -\hline \end{tabular} \end{center} \caption{Currently allocated RISC-V hypervisor-level CSR addresses.} @@ -276,6 +270,7 @@ Number & Privilege & Name & Description \\ \tt 0x303 & MRW &\tt mideleg & Machine interrupt delegation register. \\ \tt 0x304 & MRW &\tt mie & Machine interrupt-enable register. \\ \tt 0x305 & MRW &\tt mtvec & Machine trap-handler base address. \\ +\tt 0x306 & MRW &\tt mcounteren & Machine counter enable. \\ \hline \multicolumn{4}{|c|}{Machine Trap Handling} \\ \hline @@ -327,7 +322,6 @@ Number & Privilege & Name & Description \\ \hline \multicolumn{4}{|c|}{Machine Counter Setup} \\ \hline -\tt 0x320 & MRW &\tt mcounteren & Machine counter enable. \\ \tt 0x323 & MRW &\tt mhpmevent3 & Machine performance-monitoring event selector. \\ \tt 0x324 & MRW &\tt mhpmevent4 & Machine performance-monitoring event selector. \\ & & \multicolumn{1}{c|}{\vdots} & \ \\ |