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author | Andrew Waterman <andrew@sifive.com> | 2018-04-13 01:38:04 -0700 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2018-04-13 14:08:18 -0700 |
commit | cdb665618383ec40aeac722d0c99a3e46b974a4f (patch) | |
tree | 546fc88ea8a5259a7559c53bc4eaefde4b92d1ab /src/priv-csrs.tex | |
parent | 7962ea218970f8c4c34a23e0f3b75786337b3fcf (diff) | |
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Clarifications re: writable XLEN
Diffstat (limited to 'src/priv-csrs.tex')
-rw-r--r-- | src/priv-csrs.tex | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index 003f5df..3dc2613 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -437,3 +437,31 @@ values to an \warl\ field. Implementations must always deterministically return the same legal value after a given illegal value is written. +\section{CSR Width Modulation} + +If the width of a CSR is changed (for example, by changing M-XLEN or U-XLEN, as +described in Section~\ref{xlen-control}), the values of the {\em writable} +fields and bits of the new-width CSR are, unless specified otherwise, +determined from the previous-width CSR as though by this algorithm: + +\begin{enumerate} + +\item The value of the previous-width CSR is copied to a temporary register of +the same width. + +\item For the read-only bits of the previous-width CSR, the bits at the same +positions in the temporary register are set to zeros. + +\item The width of the temporary register is changed to the new width. If the +new width $W$ is narrower than the previous width, the least-significant $W$ +bits of the temporary register are retained and the more-significant bits are +discarded. If the new width is wider than the previous width, the temporary +register is zero-extended to the wider width. + +\item Each writable field of the new-width CSR takes the value of the bits at +the same positions in the temporary register. + +\end{enumerate} + +Changing the width of a CSR is not a read or write of the CSR and thus +does not trigger any side effects. |