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| author | Andrew Waterman <andrew@sifive.com> | 2018-11-27 15:13:26 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-27 15:16:04 -0800 |
| commit | c7a81b2be5e210da2134b29aeb8e0fda1893cedd (patch) | |
| tree | 2e0bfeda63441dbd573ad2c901d09e3a3f04e1a2 /src/priv-csrs.tex | |
| parent | 83a0c2261cec419415f1e7c37c07479f79613185 (diff) | |
| download | riscv-isa-manual-c7a81b2be5e210da2134b29aeb8e0fda1893cedd.zip riscv-isa-manual-c7a81b2be5e210da2134b29aeb8e0fda1893cedd.tar.gz riscv-isa-manual-c7a81b2be5e210da2134b29aeb8e0fda1893cedd.tar.bz2 | |
Misc. address translation clarifications
Courtesy @gameboo in #205
Diffstat (limited to 'src/priv-csrs.tex')
| -rw-r--r-- | src/priv-csrs.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index 239a4f9..33651a3 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -290,7 +290,7 @@ Number & Privilege & Name & Description \\ \tt 0x343 & MRW &\tt mtval & Machine bad address or instruction. \\ \tt 0x344 & MRW &\tt mip & Machine interrupt pending. \\ \hline -\multicolumn{4}{|c|}{Machine Protection and Translation} \\ +\multicolumn{4}{|c|}{Machine Memory Protection} \\ \hline %\tt 0x380 & MRW &\tt mbase & Base register. \\ %\tt 0x381 & MRW &\tt mbound & Bound register. \\ |