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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-16 14:32:33 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-16 14:33:10 -0700 |
| commit | b8e20ea56d3a83c115ae7e6ff90c9b966a837248 (patch) | |
| tree | dbf4c7a4ac728e427ab76a39dd59a71b7d52305a /src/priv-csrs.tex | |
| parent | f467e5dfd4acb4391870b8bfcfd687a0e5d8eddc (diff) | |
| download | riscv-isa-manual-b8e20ea56d3a83c115ae7e6ff90c9b966a837248.zip riscv-isa-manual-b8e20ea56d3a83c115ae7e6ff90c9b966a837248.tar.gz riscv-isa-manual-b8e20ea56d3a83c115ae7e6ff90c9b966a837248.tar.bz2 | |
Hypervisor v0.4 draft
Courtesy @jhauser-us
Diffstat (limited to 'src/priv-csrs.tex')
| -rw-r--r-- | src/priv-csrs.tex | 29 |
1 files changed, 15 insertions, 14 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index 6b66257..445a2b7 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -231,25 +231,26 @@ Number & Privilege & Name & Description \\ \multicolumn{4}{|c|}{Hypervisor Trap Setup} \\ \hline \hline -\tt 0xA00 & HRW &\tt hstatus & Hypervisor status register. \\ -\tt 0xA02 & HRW &\tt hedeleg & Hypervisor exception delegation register. \\ -\tt 0xA03 & HRW &\tt hideleg & Hypervisor interrupt delegation register. \\ +\tt 0x600 & HRW &\tt hstatus & Hypervisor status register. \\ +\tt 0x602 & HRW &\tt hedeleg & Hypervisor exception delegation register. \\ +\tt 0x603 & HRW &\tt hideleg & Hypervisor interrupt delegation register. \\ +\tt 0x606 & SRW &\tt hcounteren & Hypervisor counter enable. \\ \hline \multicolumn{4}{|c|}{Hypervisor Protection and Translation} \\ \hline -\tt 0xA80 & HRW &\tt hgatp & Hypervisor guest address translation and protection. \\ +\tt 0x680 & HRW &\tt hgatp & Hypervisor guest address translation and protection. \\ \hline -\multicolumn{4}{|c|}{Hypervisor Background Supervisor Registers} \\ +\multicolumn{4}{|c|}{Virtual Supervisor Registers} \\ \hline -\tt 0x200 & HRW &\tt bsstatus & Background supervisor status register. \\ -\tt 0x204 & HRW &\tt bsie & Background supervisor interrupt-enable register. \\ -\tt 0x205 & HRW &\tt bstvec & Background supervisor trap handler base address. \\ -\tt 0x240 & HRW &\tt bsscratch & Background supervisor scratch register. \\ -\tt 0x241 & HRW &\tt bsepc & Background supervisor exception program counter. \\ -\tt 0x242 & HRW &\tt bscause & Background supervisor trap cause. \\ -\tt 0x243 & HRW &\tt bstval & Background supervisor bad address or instruction. \\ -\tt 0x244 & HRW &\tt bsip & Background supervisor interrupt pending. \\ -\tt 0x280 & HRW &\tt bsatp & Background supervisor address translation and protection. \\ +\tt 0x200 & HRW &\tt vsstatus & Virtual supervisor status register. \\ +\tt 0x204 & HRW &\tt vsie & Virtual supervisor interrupt-enable register. \\ +\tt 0x205 & HRW &\tt vstvec & Virtual supervisor trap handler base address. \\ +\tt 0x240 & HRW &\tt vsscratch & Virtual supervisor scratch register. \\ +\tt 0x241 & HRW &\tt vsepc & Virtual supervisor exception program counter. \\ +\tt 0x242 & HRW &\tt vscause & Virtual supervisor trap cause. \\ +\tt 0x243 & HRW &\tt vstval & Virtual supervisor bad address or instruction. \\ +\tt 0x244 & HRW &\tt vsip & Virtual supervisor interrupt pending. \\ +\tt 0x280 & HRW &\tt vsatp & Virtual supervisor address translation and protection. \\ \hline \end{tabular} \end{center} |