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author | Andrew Waterman <aswaterman@gmail.com> | 2017-12-28 00:55:56 -0800 |
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committer | GitHub <noreply@github.com> | 2017-12-28 00:55:56 -0800 |
commit | a33c4d6be2f2f5326be74fed85afd9deea5c5887 (patch) | |
tree | 9bf449ad52e67595b7afcfcad1103fbc02837dfe /src/priv-csrs.tex | |
parent | c66b159dbf56e0822c528beeac1142dcde443209 (diff) | |
download | riscv-isa-manual-a33c4d6be2f2f5326be74fed85afd9deea5c5887.zip riscv-isa-manual-a33c4d6be2f2f5326be74fed85afd9deea5c5887.tar.gz riscv-isa-manual-a33c4d6be2f2f5326be74fed85afd9deea5c5887.tar.bz2 |
WIRI/WPRI fields should be hardwired to 0 (#121)
Diffstat (limited to 'src/priv-csrs.tex')
-rw-r--r-- | src/priv-csrs.tex | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index e13e96a..003f5df 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -374,16 +374,20 @@ Some read-only and read/write registers have read-only fields reserved for future use. These reserved read-only fields should be ignored on a read. Writes to these fields have no effect, unless the whole CSR is read-only, in which case writes might raise an illegal instruction -exception. These fields are labeled \wiri\ in the register -descriptions. +exception. +For forward compatibility, implementations that do not furnish these fields +must hardwire them to zero. +These fields are labeled \wiri\ in the register descriptions. \subsection*{Reserved Writes Preserve Values, Reads Ignore Values (WPRI)} Some whole read/write fields are reserved for future use. Software should ignore the values read from these fields, and should preserve the values held in these fields when writing values to other fields of -the same register. These fields are labeled \wpri\ in the register -descriptions. +the same register. +For forward compatibility, implementations that do not furnish these fields +must hardwire them to zero. +These fields are labeled \wpri\ in the register descriptions. \begin{commentary} To simplify the software model, any backward-compatible future |