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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-19 23:30:45 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-21 09:03:12 -0500 |
| commit | 5da416c96963e3831e2380d8c34a1c061370ad56 (patch) | |
| tree | 90138ddcd589f96edec08eca1089f17000ce579c /src/priv-csrs.tex | |
| parent | 932da79b24f92f4a45a7d55a3ace0b8fa94036ad (diff) | |
| download | riscv-isa-manual-5da416c96963e3831e2380d8c34a1c061370ad56.zip riscv-isa-manual-5da416c96963e3831e2380d8c34a1c061370ad56.tar.gz riscv-isa-manual-5da416c96963e3831e2380d8c34a1c061370ad56.tar.bz2 | |
Move N extension into its own chapter in the priv spec
Diffstat (limited to 'src/priv-csrs.tex')
| -rw-r--r-- | src/priv-csrs.tex | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index dad890b..fe78bab 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -1,4 +1,5 @@ \chapter{Control and Status Registers (CSRs)} +\label{chap:priv-csrs} The SYSTEM major opcode is used to encode all privileged instructions in the RISC-V ISA. These can be divided into two main classes: those |