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| author | Paolo Bonzini <pbonzini@redhat.com> | 2019-07-31 09:15:32 +0200 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-08-16 14:14:12 -0700 |
| commit | 4bfae7862e436ce67c1aebaf2d95f0d35c658c51 (patch) | |
| tree | 90ac3a5d6468d635f05e4f862f7e5ab12639fa84 /src/priv-csrs.tex | |
| parent | 81300f89c4ac5f49b052b42ffe70924218d69a33 (diff) | |
| download | riscv-isa-manual-4bfae7862e436ce67c1aebaf2d95f0d35c658c51.zip riscv-isa-manual-4bfae7862e436ce67c1aebaf2d95f0d35c658c51.tar.gz riscv-isa-manual-4bfae7862e436ce67c1aebaf2d95f0d35c658c51.tar.bz2 | |
hypervisor: add performance counter delta registers
It has been requested that we add htimedelta[h] CSRs so that hosts can
lie to guests about the current time, without requiring trapping and
emulating. cycle is also included, since the SBI set timer callback has
absolute cycles as the argument. There is no intent to add equivalent
CSRs for instret and performance counters.
Fixes: #298
Diffstat (limited to 'src/priv-csrs.tex')
| -rw-r--r-- | src/priv-csrs.tex | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index fe78bab..166ff06 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -241,6 +241,11 @@ Number & Privilege & Name & Description \\ \hline \tt 0x680 & HRW &\tt hgatp & Hypervisor guest address translation and protection. \\ \hline +\multicolumn{4}{|c|}{Hypervisor Counter/Timer Virtualization Registers} \\ +\hline +\tt 0x605 & HRW &\tt htimedelta & Delta for VS/VU-mode timer. \\ +\tt 0x615 & HRW &\tt htimedeltah & Upper 32 bits of {\tt htimedelta}, RV32I only. \\ +\hline \multicolumn{4}{|c|}{Virtual Supervisor Registers} \\ \hline \tt 0x200 & HRW &\tt vsstatus & Virtual supervisor status register. \\ |