Clarify behavior of explicit accesses to CSRs wider than XLEN

h/t @jhauser-us

1 files changed, 22 insertions, 0 deletions

diff --git a/src/priv-csrs.adoc b/src/priv-csrs.adoc
index 7b3404e..1765335 100644
--- a/src/priv-csrs.adoc
+++ b/src/priv-csrs.adoc
@@ -982,3 +982,25 @@ at the same positions in the temporary register.
 
 Changing the width of a CSR is not a read or write of the CSR and thus
 does not trigger any side effects.
+
+=== Explicit Accesses to CSRs Wider than XLEN
+
+If a standard CSR is wider than XLEN bits, then an explicit read
+of the CSR returns the register's least-significant XLEN bits,
+and an explicit write to the CSR modifies only the register's
+least-significant XLEN bits, leaving the upper bits unchanged.
+
+Some standard CSRs, such as the counter CSRs of extension
+Zicntr, are always 64 bits, even when XLEN=32 (RV32).
+For each such 64-bit CSR (for example, counter `time`),
+a corresponding 32-bit _high-half CSR_ is usually defined with
+the same name but with the letter '`h`' appended at the end (`timeh`).
+The high-half CSR aliases bits 63:32 of its namesake
+64-bit CSR, thus providing a way for RV32 software
+to read and modify the otherwise-unreachable 32 bits.
+
+Standard high-half CSRs are accessible only when
+the base RISC-V instruction set is RV32 (XLEN=32).
+For RV64 (when XLEN=64), the addresses of all standard high-half CSRs
+are reserved, so an attempt to access a high-half CSR
+typically raises an illegal instruction exception.