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| author | wmat <wmat@riscv.org> | 2024-04-05 15:49:12 -0400 |
|---|---|---|
| committer | wmat <wmat@riscv.org> | 2024-04-05 15:49:12 -0400 |
| commit | 0e00b8f74c91a22eea2d0c788aacb81a89ab558f (patch) | |
| tree | 3fcdc2d6409b35d4dae1947221c81baa66837fd1 /src/priv-csrs.adoc | |
| parent | 7d560d38d05416d5a79224b0178033de09beb5cd (diff) | |
| download | riscv-isa-manual-0e00b8f74c91a22eea2d0c788aacb81a89ab558f.zip riscv-isa-manual-0e00b8f74c91a22eea2d0c788aacb81a89ab558f.tar.gz riscv-isa-manual-0e00b8f74c91a22eea2d0c788aacb81a89ab558f.tar.bz2 | |
Moving note about draft Zam extension to unpriv preface.
Moving the note about the Zam extension to the unpriv preface.
Diffstat (limited to 'src/priv-csrs.adoc')
| -rw-r--r-- | src/priv-csrs.adoc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/priv-csrs.adoc b/src/priv-csrs.adoc index 85149f2..a414e81 100644 --- a/src/priv-csrs.adoc +++ b/src/priv-csrs.adoc @@ -83,11 +83,12 @@ Note that not all registers are required on all implementations. [[csrrwpriv]] .Allocation of RISC-V CSR address ranges. [%autowidth,float="center",align="center",cols="^,^,^,^,<,<,<,<"] +[.monofont] |=== 3+^|CSR Address 2.2+|Hex 3.2+|Use and Accessibility |[11:10] |[9:8] |[7:4] 8+|Unprivileged and User-Level CSRs -|`00` |`00` |`XXXX` 2+| `0x000-0x0FF` 3+|Standard read/write +m|00 m|00 m|XXXX 2+m| 0x000-0x0FF 3+|Standard read/write |`01` |`00` |`XXXX` 2+| `0x400-0x4FF` 3+|Standard read/write |`10` |`00` |`XXXX` 2+| `0x800-0x8FF` 3+|Custom read/write |`11` |`00` |`0XXX` 2+| `0xC00-0xC7F` 3+|Standard read-only @@ -412,6 +413,7 @@ Virtual supervisor address translation and protection. <<< [[mcsrnames0]] +[.monocell] .Currently allocated RISC-V machine-level CSR addresses. [%autowidth,float="center",align="center",cols="<,<,<,<",options="header"] |=== |