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authorAndrew Waterman <andrew@sifive.com>2019-07-23 20:06:57 -0700
committerAndrew Waterman <andrew@sifive.com>2019-07-23 20:06:57 -0700
commite87173489d7cf3818aecaf397b7e54f787cc2d31 (patch)
tree3d609706d26967fddb4dc26417e5e2b7c696fece /src/naming.tex
parent5da416c96963e3831e2380d8c34a1c061370ad56 (diff)
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Fix extension ordering in naming chapter and preface
Diffstat (limited to 'src/naming.tex')
-rw-r--r--src/naming.tex7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/naming.tex b/src/naming.tex
index e0d35b5..2006d80 100644
--- a/src/naming.tex
+++ b/src/naming.tex
@@ -130,7 +130,8 @@ alphabetical name and an optional version number.
For example, ``Xhwacha'' names the Hwacha vector-fetch ISA extension;
``Xhwacha2'' and ``Xhwacha2p0'' name version 2.0 of same.
-Non-standard extensions must be separated from other multi-letter extensions
+Non-standard extensions must be listed after all standard extensions.
+They must be separated from other multi-letter extensions
by an underscore. For example, an ISA with non-standard extensions
Argle and Bargle may be named ``RV64IZifencei\_Xargle\_Xbargle''.
@@ -159,8 +160,6 @@ Integer Multiplication and Division & M & \\
Atomics & A & \\
Single-Precision Floating-Point & F & Zicsr \\
Double-Precision Floating-Point & D & F \\
-Control and Status Register Access & Zicsr & \\
-Instruction-Fetch Fence & Zifencei & \\
\hline
General & G & IMADZifencei \\
\hline
@@ -173,6 +172,8 @@ Transactional Memory & T & \\
Packed-SIMD Extensions & P & \\
Vector Extensions & V & \\
User-Level Interrupts & N & \\
+Control and Status Register Access & Zicsr & \\
+Instruction-Fetch Fence & Zifencei & \\
Misaligned Atomics & Zam & A \\
Total Store Ordering & Ztso & \\
\hline