fixes to appendices, tables and graphics

1 files changed, 97 insertions, 91 deletions

diff --git a/src/mm-eplan.adoc b/src/mm-eplan.adoc
index 1fde4c9..7b8ec81 100644
--- a/src/mm-eplan.adoc
+++ b/src/mm-eplan.adoc
@@ -660,6 +660,8 @@ enforces ordering with respect to all previous loads.
 
 [[spinlock_atomics]]
 .A spinlock with atomics
+[source%linenums,asm]
+[source%linenums,asm]
 ....
           sd           x1, (a1)     # Arbitrary unrelated store
           ld           x2, (a2)     # Arbitrary unrelated load
@@ -685,6 +687,7 @@ load` at the beginning of the example in the global memory order.
 
 [[spinlock_fences]]
 .A spinlock with fences
+[source%linenums,asm]
 ....
           sd           x1, (a1)     # Arbitrary unrelated store
           ld           x2, (a2)     # Arbitrary unrelated load
@@ -786,6 +789,7 @@ _rs1_ to _rd_.
 
 [[fflags]]
 .(c) has a syntactic dependency on both (a) and (b) via fflags, a destination register that both (a) and (b) implicitly accumulate into
+[source%linenums,asm]
 ....
 (a) fadd f3,f1,f2
 (b) fadd f6,f4,f5
@@ -809,6 +813,7 @@ syntactic dependencies as a lightweight ordering mechanism.
 
 [[address]]
 .A syntactic address dependency
+[source%linenums,asm]
 ....
 ld a1,0(s0)
 xor a2,a1,a1
@@ -835,6 +840,7 @@ expensive.
 
 [[control1]]
 .A syntactic control dependency
+[source%linenums,asm]
 ....
 	lw x1,0(x2)
 	bne x1,x0,next
@@ -852,6 +858,7 @@ dependency from the memory operation generated by the first instruction.
 
 [[control2]]
 .Another syntactic control dependency
+[source%linenums,asm]
 ....
 lw x1,0(x2)
 bne x1,x0,next
@@ -1148,14 +1155,14 @@ those external devices and buses.
 
 [[tsomappings]]
 .Mappings from TSO operations to RISC-V operations
-[cols="<,<",options="header",]
+[cols="<,<",options="header",separator=!]
 |===
-|x86/TSO Operation |RVWMO Mapping
-|Load | `l{b|h|w|d}; fence r,rw`
-|Store |`fence rw,w; s{b|h|w|d}`
-|Atomic RMW |`amo<op>.{w|d}.aqrl OR`
-| |`loop:lr.{w|d}.aq; <op>; sc.{w|d}.aqrl; bnez loop`
-|Fence |`fence rw,rw`
+!x86/TSO Operation !RVWMO Mapping
+!Load ! `l{b|h|w|d}; fence r,rw`
+!Store !`fence rw,w; s{b|h|w|d}`
+!Atomic RMW !`amo<op>.{w|d}.aqrl OR`
+! !`loop:lr.{w|d}.aq; <op>; sc.{w|d}.aqrl; bnez loop`
+!Fence !`fence rw,rw`
 |===
 
 <<somappings>> provides a mapping from TSO memory
@@ -1184,16 +1191,16 @@ reservation mechanism than was originally intended.
 
 [[powermappings]]
 .Mappings from Power operations to RISC-V operations
-[cols="<,<",options="header",]
+[cols="<,<",options="header",separator=!]
 |===
-|Power Operation |RVWMO Mapping
-|Load |`l{b|h|w|d}`
-|Load-Reserve |`lr.{w|d}`
-|Store |`s{b|h|w|d}`
-|Store-Conditional |`sc.{w|d}`
-|`lwsync` |`fence.tso`
-|`sync` |`fence rw,rw`
-|`isync` |`fence.i; fence r,r`
+!Power Operation !RVWMO Mapping
+!Load !`l{b|h|w|d}`
+!Load-Reserve !`lr.{w|d}`
+!Store !`s{b|h|w|d}`
+!Store-Conditional !`sc.{w|d}`
+!`lwsync` !`fence.tso`
+!`sync` !`fence rw,rw`
+!`isync` !`fence.i; fence r,r`
 |===
 
 <<powermappings>> provides a mapping from Power memory
@@ -1204,21 +1211,21 @@ not present in RVWMO.
 
 [[armmappings]]
 .Mappings from ARM operations to RISC-V operations
-[cols="<,<",options="header",]
+[cols="<,<",options="header",separator=!]
 |===
-|ARM Operation |RVWMO Mapping
-|Load |`l{b|h|w|d}`
-|Load-Acquire |`fence rw, rw; l{b|h|w|d}; fence r,rw`
-|Load-Exclusive |`lr.{w|d}`
-|Load-Acquire-Exclusive |`lr.{w|d}.aqrl`
-|Store |`s{b|h|w|d}`
-|Store-Release |`fence rw,w; s{b|h|w|d}`
-|Store-Exclusive |`sc.{w|d}`
-|Store-Release-Exclusive |`sc.{w|d}.rl`
-|`dmb` |`fence rw,rw`
-|`dmb.ld` |`fence r,rw`
-|`dmb.st` |`fence w,w`
-|`isb` |`fence.i; fence r,r`
+!ARM Operation !RVWMO Mapping
+!Load !`l{b|h|w|d}`
+!Load-Acquire !`fence rw, rw; l{b|h|w|d}; fence r,rw`
+!Load-Exclusive !`lr.{w|d}`
+!Load-Acquire-Exclusive !`lr.{w|d}.aqrl`
+!Store !`s{b|h|w|d}`
+!Store-Release !`fence rw,w; s{b|h|w|d}`
+!Store-Exclusive !`sc.{w|d}`
+!Store-Release-Exclusive !`sc.{w|d}.rl`
+!`dmb` !`fence rw,rw`
+!`dmb.ld` !`fence r,rw`
+!`dmb.st` !`fence w,w`
+!`isb` !`fence.i; fence r,r`
 |===
 
 <<armmappings>> provides a mapping from ARM memory
@@ -1337,6 +1344,7 @@ Memory Model evolves.
 
 [[lkmm_ll]]
 .Orderings between critical sections in Linux
+[source%linenums,asm]
 ....
 (a) int r0 = *x;
 (bc) spin_unlock(y, 0);
@@ -1364,128 +1372,126 @@ _aq_ and _rl_ set.
 
 [[c11mappings]]
 .Mappings from C/C++ primitives to RISC-V primitives.
-[cols="<,<",options="header",]
+[cols="<,<",options="header",separator=!]
 |===
-|C/C++ Construct | RVWMO Mapping
 
-|Non-atomic load | `l{b|h|w|d}`
+!C/C++ Construct ! RVWMO Mapping
+
+!Non-atomic load ! `l{b|h|w|d}`
 
-|`atomic_load(memory_order_relaxed)` |`l{b|h|w|d}`
+!`atomic_load(memory_order_relaxed)` !`l{b|h|w|d}`
 
-|`atomic_load(memory_order_acquire)` |`l{b|h|w|d}; fence r,rw`
+!`atomic_load(memory_order_acquire)` !`l{b|h|w|d}; fence r,rw`
 
-|`atomic_load(memory_order_seq_cst)` |`fence rw,rw; l{b|h|w|d}; fence r,rw`
+!`atomic_load(memory_order_seq_cst)` !`fence rw,rw; l{b|h|w|d}; fence r,rw`
 
-|Non-atomic store |`s{b|h|w|d}`
+!Non-atomic store !`s{b|h|w|d}`
 
-|`atomic_store(memory_order_relaxed)` |`s{b|h|w|d}`
+!`atomic_store(memory_order_relaxed)` !`s{b|h|w|d}`
 
-|`atomic_store(memory_order_release)` |`fence rw,w; s{b|h|w|d}`
+!`atomic_store(memory_order_release)` !`fence rw,w; s{b|h|w|d}`
 
-|`atomic_store(memory_order_seq_cst)` |`fence rw,w; s{b|h|w|d}`
+!`atomic_store(memory_order_seq_cst)` !`fence rw,w; s{b|h|w|d}`
 
-|`atomic_thread_fence(memory_order_acquire)` |`fence r,rw`
+!`atomic_thread_fence(memory_order_acquire)` !`fence r,rw`
 
-|`atomic_thread_fence(memory_order_release)` |`fence rw,w`
+!`atomic_thread_fence(memory_order_release)` !`fence rw,w`
 
-|`atomic_thread_fence(memory_order_acq_rel)` |`fence.tso`
+!`atomic_thread_fence(memory_order_acq_rel)` !`fence.tso`
 
-|`atomic_thread_fence(memory_order_seq_cst)` |`fence rw,rw`
+!`atomic_thread_fence(memory_order_seq_cst)` !`fence rw,rw`
 
-|C/C++ Construct |RVWMO AMO Mapping
+!C/C++ Construct !RVWMO AMO Mapping
 
-|`atomic_<op>(memory_order_relaxed)` |`amo<op>.{w|d}`
+!`atomic_<op>(memory_order_relaxed)` !`amo<op>.{w|d}`
 
-|`atomic_<op>(memory_order_acquire)` |`amo<op>.{w|d}.aq`
+!`atomic_<op>(memory_order_acquire)` !`amo<op>.{w|d}.aq`
 
-|`atomic_<op>(memory_order_release)` |`amo<op>.{w|d}.rl`
+!`atomic_<op>(memory_order_release)` !`amo<op>.{w|d}.rl`
 
-|`atomic_<op>(memory_order_acq_rel)` |`amo<op>.{w|d}.aqrl`
+!`atomic_<op>(memory_order_acq_rel)` !`amo<op>.{w|d}.aqrl`
 
-|`atomic_<op>(memory_order_seq_cst)` |`amo<op>.{w|d}.aqrl`
+!`atomic_<op>(memory_order_seq_cst)` !`amo<op>.{w|d}.aqrl`
 
-|C/C++ Construct |RVWMO LR/SC Mapping
+!C/C++ Construct !RVWMO LR/SC Mapping
 
-|`atomic_<op>(memory_order_relaxed)` |`loop:lr.{w|d}; <op>; sc.{w|d};`
+!`atomic_<op>(memory_order_relaxed)` !`loop:lr.{w|d}; <op>; sc.{w|d};`
 
-| |`bnez loop`
+! !`bnez loop`
 
-|`atomic_<op>(memory_order_acquire)`
-|`loop:lr.{w|d}.aq; <op>; sc.{w|d};`
+!`atomic_<op>(memory_order_acquire)` !`loop:lr.{w|d}.aq; <op>; sc.{w|d};`
 
-| |`bnez loop`
+! !`bnez loop`
 
-|`atomic_<op>(memory_order_release)`
-|`loop:lr.{w|d}; <op>; sc.{w|d}.rl;`
+!`atomic_<op>(memory_order_release)` !`loop:lr.{w|d}; <op>; sc.{w|d}.rl;`
 
-| |`bnez loop`
+! !`bnez loop`
 
-|`atomic_<op>(memory_order_acq_rel)`
-|`loop:lr.{w|d}.aq; <op>; sc.{w|d}.rl;`
+!`atomic_<op>(memory_order_acq_rel)` !`loop:lr.{w|d}.aq; <op>; sc.{w|d}.rl;`
 
-| |`bnez loop`
+! !`bnez loop`
 
-|`atomic_<op>(memory_order_seq_cst)` |`loop:lr.{w|d}.aqrl; <op>;`
+!`atomic_<op>(memory_order_seq_cst)` !`loop:lr.{w|d}.aqrl; <op>;`
 
-| |`sc.{w|d}.rl; bnez loop`
+! !`sc.{w|d}.rl; bnez loop`
 
 |===
 
 [[c11mappings_hypothetical]]
 .Hypothetical mappings from C/C++ primitives to RISC-V primitives, if native load-acquire and store-release opcodes are introduced.
-[cols="<,<",options="header",]
+[cols="<,<",options="header",separator=!]
 |===
-|C/C++ Construct |RVWMO Mapping
+!C/C++ Construct !RVWMO Mapping
 
-|Non-atomic load |`l{b|h|w|d}`
+!Non-atomic load !`l{b|h|w|d}`
 
-|`atomic_load(memory_order_relaxed)` |`l{b|h|w|d}`
+!`atomic_load(memory_order_relaxed)` !`l{b|h|w|d}`
 
-|`atomic_load(memory_order_acquire)` |`l{b|h|w|d}.aq`
+!`atomic_load(memory_order_acquire)` !`l{b|h|w|d}.aq`
 
-|`atomic_load(memory_order_seq_cst)` |`l{b|h|w|d}.aq`
+!`atomic_load(memory_order_seq_cst)` !`l{b|h|w|d}.aq`
 
-|Non-atomic store |`s{b|h|w|d}`
+!Non-atomic store !`s{b|h|w|d}`
 
-|`atomic_store(memory_order_relaxed)` |`s{b|h|w|d}`
+!`atomic_store(memory_order_relaxed)` !`s{b|h|w|d}`
 
-|`atomic_store(memory_order_release)` |`s{b|h|w|d}.rl`
+!`atomic_store(memory_order_release)` !`s{b|h|w|d}.rl`
 
-|`atomic_store(memory_order_seq_cst)` |`s{b|h|w|d}.rl`
+!`atomic_store(memory_order_seq_cst)` !`s{b|h|w|d}.rl`
 
-|`atomic_thread_fence(memory_order_acquire)` |`fence r,rw`
+!`atomic_thread_fence(memory_order_acquire)` !`fence r,rw`
 
-|`atomic_thread_fence(memory_order_release)` |`fence rw,w`
+!`atomic_thread_fence(memory_order_release)` !`fence rw,w`
 
-|`atomic_thread_fence(memory_order_acq_rel)` |`fence.tso`
+!`atomic_thread_fence(memory_order_acq_rel)` !`fence.tso`
 
-|`atomic_thread_fence(memory_order_seq_cst)` |`fence rw,rw`
+!`atomic_thread_fence(memory_order_seq_cst)` !`fence rw,rw`
 
-|C/C++ Construct |RVWMO AMO Mapping
+!C/C++ Construct !RVWMO AMO Mapping
 
-|`atomic_<op>(memory_order_relaxed)` |`amo<op>.{w|d}`
+!`atomic_<op>(memory_order_relaxed)` !`amo<op>.{w|d}`
 
-|`atomic_<op>(memory_order_acquire)` |`amo<op>.{w|d}.aq`
+!`atomic_<op>(memory_order_acquire)` !`amo<op>.{w|d}.aq`
 
-|`atomic_<op>(memory_order_release)` |`amo<op>.{w|d}.rl`
+!`atomic_<op>(memory_order_release)` !`amo<op>.{w|d}.rl`
 
-|`atomic_<op>(memory_order_acq_rel)` |`amo<op>.{w|d}.aqrl`
+!`atomic_<op>(memory_order_acq_rel)` !`amo<op>.{w|d}.aqrl`
 
-|`atomic_<op>(memory_order_seq_cst)` |`amo<op>.{w|d}.aqrl`
+!`atomic_<op>(memory_order_seq_cst)` !`amo<op>.{w|d}.aqrl`
 
-|C/C++ Construct |RVWMO LR/SC Mapping
+!C/C++ Construct !RVWMO LR/SC Mapping
 
-|`atomic_<op>(memory_order_relaxed)` |`lr.{w|d}; <op>; sc.{w|d}`
+!`atomic_<op>(memory_order_relaxed)` !`lr.{w|d}; <op>; sc.{w|d}`
 
-|`atomic_<op>(memory_order_acquire)` |`lr.{w|d}.aq; <op>; sc.{w|d}`
+!`atomic_<op>(memory_order_acquire)` !`lr.{w|d}.aq; <op>; sc.{w|d}`
 
-|`atomic_<op>(memory_order_release)` |`lr.{w|d}; <op>; sc.{w|d}.rl`
+!`atomic_<op>(memory_order_release)` !`lr.{w|d}; <op>; sc.{w|d}.rl`
 
-|`atomic_<op>(memory_order_acq_rel)` |`lr.{w|d}.aq; <op>; sc.{w|d}.rl`
+!`atomic_<op>(memory_order_acq_rel)` !`lr.{w|d}.aq; <op>; sc.{w|d}.rl`
 
-|`atomic_<op>(memory_order_seq_cst)` |`lr.{w|d}.aq^&#2731; <op>; sc.{w|d}.rl`
+!`atomic_<op>(memory_order_seq_cst)` !`lr.{w|d}.aq^&#2731; <op>; sc.{w|d}.rl`
 
-|`^&#2731;` must be `lr.{w|d}.aqrl` in order to interoperate with code mapped per <<c11mappings>> |
+!`^&#2731;` must be `lr.{w|d}.aqrl` in order to interoperate with code mapped per <<c11mappings>> !
 |===
 
 Any AMO can be emulated by an LR/SC pair, but care must be taken to