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| author | Alexandre Joannou <gameboo@users.noreply.github.com> | 2018-05-02 23:30:03 +0100 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-05-02 15:30:03 -0700 |
| commit | 3559c11db55e96e1220c6b032d9d920b1808f151 (patch) | |
| tree | 382a14fd5140eb235138683b2b45811571ca8512 /src/memory.tex | |
| parent | 64786dec5330b6618fd0e0f63bd34bf399075beb (diff) | |
| download | riscv-isa-manual-3559c11db55e96e1220c6b032d9d920b1808f151.zip riscv-isa-manual-3559c11db55e96e1220c6b032d9d920b1808f151.tar.gz riscv-isa-manual-3559c11db55e96e1220c6b032d9d920b1808f151.tar.bz2 | |
Clarify URET with no user-mode traps support (#164)
* Explicitly raise an illegal instruction exception for URET with no user-mode traps
* Folding aswaterman comment about SRET and redundant text.
Diffstat (limited to 'src/memory.tex')
0 files changed, 0 insertions, 0 deletions