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authorAndrew Waterman <andrew@sifive.com>2021-10-04 16:45:29 -0700
committerAndrew Waterman <andrew@sifive.com>2021-10-04 16:45:46 -0700
commit22c8813c7a05bd9d54892995b43e95f25f9df883 (patch)
tree6620e0143b2bff7bb438469c20e659bdbac170f4 /src/machine.tex
parent6d363324263680bbd5e8a6ed16d2f2d42c63913f (diff)
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Clarify order in which PMP CSRs must be implemented
Diffstat (limited to 'src/machine.tex')
-rw-r--r--src/machine.tex3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex
index 043d584..2ae1756 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -3346,7 +3346,8 @@ PMP entries are described by an 8-bit configuration register and one MXLEN-bit
address register. Some PMP settings additionally use the address register
associated with the preceding PMP entry.
Up to 64 PMP entries are supported.
-Implementations may implement zero, 16, or 64 PMP CSRs.
+Implementations may implement zero, 16, or 64 PMP CSRs; the lowest-numbered
+PMP CSRs must be implemented first.
All PMP CSR fields are \warl\ and may be hardwired to zero.
PMP CSRs are only accessible to M-mode.