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| author | Andrew Waterman <andrew@sifive.com> | 2021-11-29 18:24:59 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-11-29 18:24:59 -0800 |
| commit | f88f6b883f864890efbc1fcab58aa8e29066bee4 (patch) | |
| tree | 9e0512844be1ff23e78bc931c60ba67156443a17 /src/machine.tex | |
| parent | 682593e84284ece836a4fea0a226264b77292d72 (diff) | |
| download | riscv-isa-manual-f88f6b883f864890efbc1fcab58aa8e29066bee4.zip riscv-isa-manual-f88f6b883f864890efbc1fcab58aa8e29066bee4.tar.gz riscv-isa-manual-f88f6b883f864890efbc1fcab58aa8e29066bee4.tar.bz2 | |
Add menvcfg.PBMTE / henvcfg.PBMTE
Architecture Review of the Svpbmt extension concluded that adding a
mechanism to disable availability of Svpbmt was desirable, because
(for example) if a hypervisor can know with certainty that its guest
cannot modify the memory attributes, then it can avoid cache flushing
in certain device-emulation regimes.
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/src/machine.tex b/src/machine.tex index 110fab1..61c143f 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2325,9 +2325,10 @@ for modes less privileged than M. \begin{figure}[h!] {\footnotesize \begin{center} -\begin{tabular}{c@{}Kcc@{}W@{}Wc} +\begin{tabular}{cc@{}Mcc@{}W@{}Wc} \instbit{63} & -\instbitrange{62}{8} & +\instbit{62} & +\instbitrange{61}{8} & \instbit{7} & \instbit{6} & \instbitrange{5}{4} & @@ -2335,6 +2336,7 @@ for modes less privileged than M. \instbit{0} \\ \hline \multicolumn{1}{|c|}{STCE} & +\multicolumn{1}{c|}{PBMTE} & \multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{CBZE} & \multicolumn{1}{c|}{CBCFE} & @@ -2342,7 +2344,7 @@ for modes less privileged than M. \multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{FIOM} \\ \hline -1 & 55 & 1 & 1 & 2 & 3 & 1 \\ +1 & 1 & 54 & 1 & 1 & 2 & 3 & 1 \\ \end{tabular} \end{center} } @@ -2395,6 +2397,14 @@ hypervisor extension of Chapter~\ref{hypervisor}, which has an equivalent FIOM bit in the hypervisor CSR {\tt henvcfg}. \end{commentary} +The PBMTE bit controls whether the Svpbmt extension is available for use in +S-mode and G-stage address translation (i.e., for page tables pointed to by +{\tt satp} or {\tt hgatp}). +When PBMTE=1, Svpbmt is available for S-mode and G-stage address translation. +When PBMTE=0, the implementation behaves as though Svpbmt were not implemented. +Furthermore, for implementations with the hypervisor extension, +{\tt henvcfg}.PBMTE is read-only zero if {\tt menvcfg}.PBMTE is zero. + The definition of the STCE field will be furnished by the forthcoming Sstc extension. Its allocation within {\tt menvcfg} may change prior to the ratification |