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| author | Andrew Waterman <andrew@sifive.com> | 2021-09-11 01:11:18 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-09-11 01:11:18 -0700 |
| commit | f864c377eb9d576f66d1c641bb389623033f7c9a (patch) | |
| tree | 22947674286828693fe285fa36213d180bb9e7c1 /src/machine.tex | |
| parent | 01069ac96b90bdc330fc4471945639a54e3b3b69 (diff) | |
| download | riscv-isa-manual-f864c377eb9d576f66d1c641bb389623033f7c9a.zip riscv-isa-manual-f864c377eb9d576f66d1c641bb389623033f7c9a.tar.gz riscv-isa-manual-f864c377eb9d576f66d1c641bb389623033f7c9a.tar.bz2 | |
Rename STCE to STCD to reverse its polarity
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index adf9657..fece762 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2312,7 +2312,7 @@ for modes less privileged than M. \instbitrange{3}{1} & \instbit{0} \\ \hline -\multicolumn{1}{|c|}{STCD} & +\multicolumn{1}{|c|}{STCE} & \multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{CBZE} & \multicolumn{1}{c|}{CBCFE} & @@ -2373,7 +2373,7 @@ hypervisor extension of Chapter~\ref{hypervisor}, which has an equivalent FIOM bit in the hypervisor CSR {\tt henvcfg}. \end{commentary} -The definition of the STCD field will be furnished by the +The definition of the STCE field will be furnished by the forthcoming Sstc extension. Its allocation within {\tt menvcfg} may change prior to the ratification of that extension. |