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| author | Andrew Waterman <andrew@sifive.com> | 2021-10-25 14:28:24 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-10-25 14:28:54 -0700 |
| commit | dbdea6b06f031a500a4c8ff3fcd52d0dfab2574e (patch) | |
| tree | d628cc72d1b697c1d4ee6f6eeb34cd2830651dd4 /src/machine.tex | |
| parent | 399c9a759eb4540a65c60e2cc236164821ff2346 (diff) | |
| download | riscv-isa-manual-dbdea6b06f031a500a4c8ff3fcd52d0dfab2574e.zip riscv-isa-manual-dbdea6b06f031a500a4c8ff3fcd52d0dfab2574e.tar.gz riscv-isa-manual-dbdea6b06f031a500a4c8ff3fcd52d0dfab2574e.tar.bz2 | |
No valid LR/SC reservation upon reset
Closes #758
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index 93b16e4..a5e7037 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2810,6 +2810,8 @@ If little-endian memory accesses are supported, the {\tt mstatus}/{\tt mstatush} field MBE is reset to 0. The {\tt misa} register is reset to enable the maximal set of supported extensions and widest MXLEN, as described in Section~\ref{sec:misa}. +For implementations with the ``A'' standard extension, there is no valid load +reservation. The {\tt pc} is set to an implementation-defined reset vector. The {\tt mcause} register is set to a value indicating the cause of the reset. |