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| author | Andrew Waterman <andrew@sifive.com> | 2021-09-21 19:21:49 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-09-21 19:22:58 -0700 |
| commit | d29cb13885d7dfaae9aaa27b45e44733254ead37 (patch) | |
| tree | 2a1c2820edab2a7facfb8c5076e9b96b23ebdf15 /src/machine.tex | |
| parent | 9b46f474bd8e02f60ecafc4c59a5e95aace9bf81 (diff) | |
| download | riscv-isa-manual-d29cb13885d7dfaae9aaa27b45e44733254ead37.zip riscv-isa-manual-d29cb13885d7dfaae9aaa27b45e44733254ead37.tar.gz riscv-isa-manual-d29cb13885d7dfaae9aaa27b45e44733254ead37.tar.bz2 | |
Add example to clarify mip.SEIP behavior
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index 3472d44..043d584 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1555,6 +1555,14 @@ Only the software-writable SEIP bit participates in the read-modify-write sequence of a CSRRS or CSRRC instruction. \begin{commentary} + For example, if we name the software-writable SEIP bit {\tt B} and the + signal from the external interrupt controller {\tt E}, then if \mbox{\tt csrrs + t0, mip, t1} is executed, {\tt t0[9]} is written with \mbox{\tt B || E}, then + {\tt B} is written with \mbox{\tt B || t1[9]}. + If \mbox{\tt csrrw t0, mip, t1} is executed, then {\tt t0[9]} is written with + \mbox{\tt B || E}, and {\tt B} is simply written with {\tt t1[9]}. + In neither case does {\tt B} depend upon {\tt E}. + The SEIP field behavior is designed to allow a higher privilege layer to mimic external interrupts cleanly, without losing any real external interrupts. The behavior of the CSR instructions is |