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| author | Andrew Waterman <andrew@sifive.com> | 2021-08-25 15:51:22 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-08-25 15:54:42 -0700 |
| commit | d068b7622ef7769fd75c637c7806092e2a505ad1 (patch) | |
| tree | 608556d6371a6361677eef2dda52a71adc67f967 /src/machine.tex | |
| parent | d978dd68b0cf885044f0b279b74e00cd79632676 (diff) | |
| download | riscv-isa-manual-d068b7622ef7769fd75c637c7806092e2a505ad1.zip riscv-isa-manual-d068b7622ef7769fd75c637c7806092e2a505ad1.tar.gz riscv-isa-manual-d068b7622ef7769fd75c637c7806092e2a505ad1.tar.bz2 | |
Remove historical remark on MRET definition
Since the N extension is gone, the comment is largely irrelevant.
The virtualization comment still partially applies, because we wish
to be able to virtualize M/HS inside S/VS, but has also become less
relevant because of the TSR feature in mstatus.
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/machine.tex b/src/machine.tex index 6e52218..0f00279 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2466,15 +2466,6 @@ mode stack. In addition to manipulating the privilege stack as described in Section~\ref{privstack}, {\em x}\/RET sets the {\tt pc} to the value stored in the {\em x}\/{\tt epc} register. -\begin{commentary} -Previously, there was only a single ERET instruction (which was also -earlier known as SRET). To support the addition of user-level -interrupts, we needed to add a separate URET instruction to continue -to allow classic virtualization of OS code using the ERET instruction. -It then became more orthogonal to support a different {\em x}\/RET -instruction per privilege level. -\end{commentary} - If the A extension is supported, the {\em x}\/RET instruction is allowed to clear any outstanding LR address reservation but is not required to. Trap handlers should explicitly clear the reservation if |