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| author | Andrew Waterman <andrew@sifive.com> | 2018-11-30 13:45:40 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-30 13:45:40 -0800 |
| commit | c7793586787ed3c6f3d3cde0933341867a980d5d (patch) | |
| tree | 8bc28a11f903c62e0d559f52bf4dd6a3227eb1df /src/machine.tex | |
| parent | 62f129175c7d98d3ae9e22a004d4921b7dee6ddb (diff) | |
| download | riscv-isa-manual-c7793586787ed3c6f3d3cde0933341867a980d5d.zip riscv-isa-manual-c7793586787ed3c6f3d3cde0933341867a980d5d.tar.gz riscv-isa-manual-c7793586787ed3c6f3d3cde0933341867a980d5d.tar.bz2 | |
Revert "Clarify that bits 16 and up of *ip/*ie are "custom""
This reverts commit 6e34c135660bee09210c1af2c9502042f0998f44.
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 32 |
1 files changed, 14 insertions, 18 deletions
diff --git a/src/machine.tex b/src/machine.tex index 2e88a1f..55fdc1f 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1223,12 +1223,11 @@ bits in {\em x}\,{\tt ip} and {\em x}\,{\tt ie} appear to be hardwired to zero. \begin{figure*}[h!] -{\scriptsize +{\footnotesize \begin{center} \setlength{\tabcolsep}{4pt} -\begin{tabular}{Rccccccccccccc} -\instbitrange{MXLEN-1}{16} & -\instbitrange{15}{12} & +\begin{tabular}{Rcccccccccccc} +\instbitrange{MXLEN-1}{12} & \instbit{11} & \instbit{10} & \instbit{9} & @@ -1242,8 +1241,7 @@ to zero. \instbit{1} & \instbit{0} \\ \hline -\multicolumn{1}{|c|}{\em Res. Custom} & -\multicolumn{1}{c|}{\wpri} & +\multicolumn{1}{|c|}{\wpri} & \multicolumn{1}{c|}{MEIP} & \multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{SEIP} & @@ -1257,7 +1255,7 @@ to zero. \multicolumn{1}{c|}{SSIP} & \multicolumn{1}{c|}{USIP} \\ \hline -MXLEN-16 & 4 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\ +MXLEN-12 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\ \end{tabular} \end{center} } @@ -1267,12 +1265,11 @@ MXLEN-16 & 4 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\ \end{figure*} \begin{figure*}[h!] -{\scriptsize +{\footnotesize \begin{center} \setlength{\tabcolsep}{4pt} -\begin{tabular}{Rccccccccccccc} -\instbitrange{MXLEN-1}{16} & -\instbitrange{15}{12} & +\begin{tabular}{Rcccccccccccc} +\instbitrange{MXLEN-1}{12} & \instbit{11} & \instbit{10} & \instbit{9} & @@ -1286,8 +1283,7 @@ MXLEN-16 & 4 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\ \instbit{1} & \instbit{0} \\ \hline -\multicolumn{1}{|c|}{\em Res. Custom} & -\multicolumn{1}{c|}{\wpri} & +\multicolumn{1}{|c|}{\wpri} & \multicolumn{1}{c|}{MEIE} & \multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{SEIE} & @@ -1301,7 +1297,7 @@ MXLEN-16 & 4 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\ \multicolumn{1}{c|}{SSIE} & \multicolumn{1}{c|}{USIE} \\ \hline -MXLEN-16 & 4 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\ +MXLEN-12 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\ \end{tabular} \end{center} } @@ -1396,10 +1392,10 @@ interrupt-enable bits are hardwired to zero in the {\tt mip} and {\tt mie} registers respectively. Hence, these are all effectively \warl\ fields. -Implementations may add additional custom machine-level interrupt sources to -bits 16 and above of the {\tt mip} and {\tt mie} registers. The other -unallocated interrupt sources (15--12, 10, 6, and 2) are reserved for future -standard use. The corresponding fields are all \wpri. +Implementations may add additional platform-specific machine-level +interrupt sources to bits 16 and above of the {\tt mip} and {\tt mie} +registers. The other unallocated interrupt sources (15--12, 10, 6, and 2) +are reserved for future standard use. An interrupt {\em i} will be taken if bit {\em i} is set in both {\tt mip} and {\tt mie}, and if interrupts are globally enabled. By |