Add mseccfg CSR

1 files changed, 49 insertions, 0 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 2ed1235..5368b4a 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -2305,6 +2305,55 @@ register that is programmed by the platform or by M-mode software towards the
 beginning of the boot process.
 \end{commentary}
 
+\subsection{Machine Security Configuration Register ({\tt mseccfg})}
+\label{sec:mseccfg}
+
+{\tt mseccfg} is an optional MXLEN-bit read/write register, formatted as shown
+in Figure~\ref{fig:mseccfg}, that controls security features.
+
+When MXLEN=32 only, {\tt mseccfgh} is a 32-bit read/write register that
+contains the same fields as {\tt mseccfg} bits 63:32 when MXLEN=64.
+
+\begin{figure*}[h!]
+{\footnotesize
+\begin{center}
+\setlength{\tabcolsep}{4pt}
+\begin{tabular}{MccFccc}
+\instbitrange{XLEN-1}{10} &
+\instbit{9} &
+\instbit{8} &
+\instbitrange{7}{3} &
+\instbit{2} &
+\instbit{1} &
+\instbit{0} \\
+\hline
+\multicolumn{1}{|c|}{\wpri} &
+\multicolumn{1}{c|}{SSEED} &
+\multicolumn{1}{c|}{USEED} &
+\multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{RLB} &
+\multicolumn{1}{c|}{MMWP} &
+\multicolumn{1}{c|}{MML} \\
+\hline
+XLEN-10 & 1 & 1 & 5 & 1 & 1 & 1 \\
+\end{tabular}
+\end{center}
+}
+\vspace{-0.1in}
+\caption{Machine security configuration register ({\tt mseccfg}).}
+\label{fig:mseccfg}
+\end{figure*}
+
+The definitions of the SSEED and USEED fields will be furnished by the
+forthcoming entropy-source extension, Zkr.
+Their allocations within {\tt mseccfg} may change prior to the ratification
+of that extension.
+
+The definitions of the RLB, MMWP, and MML fields will be furnished by the
+forthcoming PMP-enhancement extension, Smepmp.
+Their allocations within {\tt mseccfg} may change prior to the ratification
+of that extension.
+
 \section{Machine-Level Memory-Mapped Registers}
 
 \subsection{Machine Timer Registers ({\tt mtime} and {\tt mtimecmp})}