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| author | Andrew Waterman <andrew@sifive.com> | 2021-08-30 19:53:26 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-08-30 19:53:26 -0700 |
| commit | 920dd97f1c605c26e3590c09f396bae9bdc51982 (patch) | |
| tree | 58a2c0961501a401fc8097b60077bd85c92b2878 /src/machine.tex | |
| parent | 46a2569962d2d65a4362427163278820acb0b453 (diff) | |
| download | riscv-isa-manual-920dd97f1c605c26e3590c09f396bae9bdc51982.zip riscv-isa-manual-920dd97f1c605c26e3590c09f396bae9bdc51982.tar.gz riscv-isa-manual-920dd97f1c605c26e3590c09f396bae9bdc51982.tar.bz2 | |
Fix constraint on existence of menvcfg[h]/FIOM
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index ae4b5f6..5280156 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2357,8 +2357,6 @@ if an atomic instruction that accesses a region ordered as device I/O has its {\em aq} and/or {\em rl} bit set, then that instruction is ordered as though it accesses both device I/O and memory. -If U-mode is not supported, FIOM is hardwired to zero. - \begin{table}[h!] \begin{center} \begin{tabular}{|c|l|} @@ -2403,6 +2401,9 @@ contains the same fields as bits 63:32 of {\tt menvcfg} when MXLEN=64. Register {\tt menvcfgh} does not exist when MXLEN=64. +If U-mode is not supported, then registers {\tt menvcfg} and {\tt menvcfgh} do +not exist. + \subsection{Machine Security Configuration Register ({\tt mseccfg})} \label{sec:mseccfg} |